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| DAVICOM Semiconductor, Inc. DM9013 10/100 Mbps 3-port Ethernet Switch Controller with General Processor Interface DATA SHEET Preliminary Version: DM9013--DS-P03 April 9, 2009 DM9013 3-port switch with Processor Interface CONTENT 1. 2. 3. 4. 5. GENERAL DESCRIPTION............................................................................................. 10 BLOCK DIAGRAM......................................................................................................... 10 FEATURES .................................................................................................................... 11 PIN CONFIGURATION : 128 PIN LQFP........................................................................ 12 PIN DESCRIPTION ........................................................................................................ 13 5.1 Processor Bus Interface ............................................................................................................................... 13 5.2 General and LED pins ................................................................................................................................... 13 5.3 P2 MII / RMII / Reverse MII Interfaces .......................................................................................................... 13 5.3.1 MII Interfaces ........................................................................................................................................... 13 5.3.2 RMII Interfaces......................................................................................................................................... 14 5.3.3 Reverse MII Interfaces ............................................................................................................................. 14 5.4 EEPROM Interfaces ....................................................................................................................................... 15 5.5 LED Pins ......................................................................................................................................................... 15 5.6 Clock Interface............................................................................................................................................... 16 5.7 Network Interface .......................................................................................................................................... 16 5.8 Miscellaneous Pins ....................................................................................................................................... 16 5.9 Power Pins ..................................................................................................................................................... 16 5.10 Strap Pins Table .......................................................................................................................................... 17 5.10.1 Strap pin in 3-port mode......................................................................................................................... 17 5.10.2 Strap pin in 2-port mode......................................................................................................................... 18 2 Preliminary datasheet DM9013-15-DS-P03 April 9, 2009 DM9013 3-port switch with Processor Interface 6. CONTROL AND STATUS REGISTER SET................................................................... 19 6.1 Network Control Register (00H) ................................................................................................................... 21 6.2 Network Status Register (01H)..................................................................................................................... 21 6.3 TX Control Register (02H)............................................................................................................................. 21 6.4 RX Control Register (05H) ............................................................................................................................ 21 6.5 RX Status Register (06H) .............................................................................................................................. 22 6.6 Receive Overflow Counter Register (07H) .................................................................................................. 22 6.7 Flow Control Register (0AH)......................................................................................................................... 22 6.8 EEPROM & PHY Control Register (0BH) ..................................................................................................... 22 6.9 EEPROM & PHY Address Register (0CH) ................................................................................................... 22 6.10 EPROM & PHY Data Register (0DH~0EH) ................................................................................................. 22 6.11 Physical Address Register (10H~15H) ...................................................................................................... 23 6.12 Multicast Address Register (16H~1DH)..................................................................................................... 23 6.13 General Purpose Control Register (1EH) .................................................................................................. 23 6.14 General Purpose Register (1FH) ................................................................................................................ 23 6.15 RX Packet Length Low Register ( 20H ) .................................................................................................... 23 6.16 RX Packet Length High Register ( 21H ) ................................................................................................... 23 6.17 RX Additional Status Register ( 26H ) ....................................................................................................... 24 6.18 RX Additional Control Register ( 27H )...................................................................................................... 24 6.19 Vendor ID Register (28H~29H) ................................................................................................................... 24 Preliminary datasheet DM9013-15-DS-P03 April 9, 2009 3 DM9013 3-port switch with Processor Interface 6.20 Product ID Register (2AH~2BH) ................................................................................................................. 24 6.21 Chip Revision Register (2CH) .................................................................................................................... 24 6.22 Transmit Control Register 2 (2DH) ............................................................................................................ 24 6.23 Transmit Check Sum Control Register (31H) ........................................................................................... 24 6.24 Receive Check Sum Control Status Register (32H)................................................................................. 25 6.25 General Purpose Control Register 2 (34H) ............................................................................................... 25 6.26 General Purpose Register 2 (35H) ............................................................................................................. 25 6.27 General Purpose Control Register 3 (36H) ............................................................................................... 25 6.28 General Purpose Register 3 (37H) ............................................................................................................. 25 6.29 Processor Data Bus driving capability Register (38H) ............................................................................ 26 6.30 Port 2 driving capability Register (3AH).................................................................................................... 26 6.31 IRQ Pin Control Register (39H) .................................................................................................................. 26 6.32 TX Block Size Control Register (3FH) ....................................................................................................... 26 6.33 Monitor Register 1 (40H) ............................................................................................................................. 27 6.34 Monitor Register 2 (41H) ............................................................................................................................. 27 6.35 Monitor Register 3 (42H) ............................................................................................................................. 27 6.36 Monitor Register 4 (43H) ............................................................................................................................. 27 6.37 Switch Control Register (52H).................................................................................................................... 27 6.38 VLAN Control Register (53H) ..................................................................................................................... 28 6.39 Switch Status Register (54H) ..................................................................................................................... 28 6.40 Bandwidth LED Control Register (55H)..................................................................................................... 28 4 Preliminary datasheet DM9013-15-DS-P03 April 9, 2009 DM9013 3-port switch with Processor Interface 6.41 Per Port Control/Status Index Register (60H)........................................................................................... 28 6.42 Per Port Control Data Register (61H) ........................................................................................................ 28 6.43 Per Port Status Data Register (62H) .......................................................................................................... 29 6.44 Per Port Forward Control Register (65H) .................................................................................................. 29 6.45 Per Port Ingress/Egress Control Register (66H) ...................................................................................... 30 6.46 Bandwidth Control Setting Register (67H)................................................................................................ 31 6.47 Per Port Block Unicast ports Control Register (68H) .............................................................................. 31 6.48 Per Port Block Multicast ports Control Register (69H)............................................................................ 31 6.49 Per Port Block Broadcast ports Control Register (6AH) ......................................................................... 31 6.50 Per Port Block Unknown ports Control Register (6BH) .......................................................................... 32 6.51 Per Port Priority Queue Control Register (6DH)....................................................................................... 32 6.52 Per Port VLAN Tag Low Byte Register (6EH) ........................................................................................... 32 6.53 Per Port VLAN Tag High Byte Register (6FH)........................................................................................... 32 6.54 MIB counter Port Index Register (80H)...................................................................................................... 32 6.55 MIB counter Data Register (81H~84H)....................................................................................................... 32 6.56 Port-based VLAN mapping table Registers (B0H~BFH).......................................................................... 33 6.57 TOS Priority Map Registers (C0H~CFH).................................................................................................... 33 6.58 VLAN Priority Map Registers (D0H~D1H) ................................................................................................. 36 6.59 Memory Data Pre-Fetch Read Command without Address Increment Register (F0H) ........................ 36 6.60 Memory Data Read Command with Address Increment Register (F2H)................................................ 36 Preliminary datasheet DM9013-15-DS-P03 April 9, 2009 5 DM9013 3-port switch with Processor Interface 6.61 Memory Data Read address Register (F4H).............................................................................................. 36 6.62 Memory Data Read address Register (F5H).............................................................................................. 37 6.63 Memory Data Write Command without Address Increment Register (F6H).......................................... 37 6.64 Memory Data Write Command with Address Increment Register (F8H) ............................................... 37 6.65 Memory Data Write address Register (FAH)............................................................................................. 37 6.66 Memory Data Write address Register (FBH)............................................................................................. 37 6.67 TX Packet Length Register (FCH~FDH) .................................................................................................... 37 6.68 Interrupt Status Register (FEH).................................................................................................................. 37 6.69 Interrupt Mask Register (FFH).................................................................................................................... 38 7. 8. EEPROM FORMAT........................................................................................................ 39 PHY REGISTERS .......................................................................................................... 42 8.1 Basic Mode Control Register (BMCR) - 00H .............................................................................................. 43 8.2 Basic Mode Status Register (BMSR) - 01H ................................................................................................ 44 8.3 PHY ID Identifier Register #1 (PHYID1) - 02H............................................................................................. 45 8.4 PHY ID Identifier Register #2 (PHYID2) - 03H............................................................................................. 45 8.5 Auto-negotiation Advertisement Register (ANAR) - 04H.......................................................................... 46 8.6 Auto-negotiation Link Partner Ability Register (ANLPAR) - 05H ............................................................. 47 8.7 Auto-negotiation Expansion Register (ANER) - 06H ................................................................................. 48 8.8 DAVICOM Specified Configuration Register (DSCR) - 10H ...................................................................... 48 8.9 DAVICOM Specified Configuration and Status Register (DSCSR) - 11H ................................................ 50 6 Preliminary datasheet DM9013-15-DS-P03 April 9, 2009 DM9013 3-port switch with Processor Interface 8.10 10BASE-T Configuration/Status (10BTCSR) - 12H.................................................................................. 51 8.11 Power Down Control Register (PWDOR) - 13H........................................................................................ 51 8.12 (Specified config) Register - 14H .............................................................................................................. 52 8.13 DAVICOM Specified Receive Error Counter Register (RECR) - 16H ..................................................... 53 8.14 DAVICOM Specified Disconnect Counter Register (DISCR) - 17H ........................................................ 53 8.15 Power Saving Control Register (PSCR) - 1DH ......................................................................................... 53 9. FUNCTIONAL DESCRIPTION....................................................................................... 54 9.1 Processor bus and memory management function: ................................................................................. 54 9.1.1 Processor Interface .................................................................................................................................. 54 9.1.2 Direct Memory Access Control................................................................................................................. 54 9.1.3 Packet Transmission................................................................................................................................ 54 9.1.4 Packet Reception ..................................................................................................................................... 54 9.2 Switch function:............................................................................................................................................. 55 9.2.1 Address Learning ..................................................................................................................................... 55 9.2.2 Address Aging .......................................................................................................................................... 55 9.2.3 Packet Forwarding ................................................................................................................................... 55 9.2.4 Inter-Packet Gap (IPG) ............................................................................................................................ 55 9.2.5 Back-off Algorithm.................................................................................................................................... 55 9.2.6 Late Collision............................................................................................................................................ 55 9.2.7 Full Duplex Flow Control .......................................................................................................................... 55 9.2.8 Half Duplex Flow Control ......................................................................................................................... 55 9.2.9 Partition Mode .......................................................................................................................................... 55 9.2.10 Broadcast Storm Filtering....................................................................................................................... 56 9.2.11 Bandwidth Control.................................................................................................................................. 56 9.2.12 Port Monitoring Support ......................................................................................................................... 56 9.2.13 VLAN Support ........................................................................................................................................ 57 9.2.13.1 Port-Based VLAN................................................................................................................................ 57 9.2.13.2 802.1Q-Based VLAN........................................................................................................................... 57 Preliminary datasheet DM9013-15-DS-P03 April 9, 2009 7 DM9013 3-port switch with Processor Interface 9.2.13.3 Tag/Untag ........................................................................................................................................... 57 9.2.14 Priority Support ...................................................................................................................................... 58 9.2.14.1 Port-Based Priority .............................................................................................................................. 58 9.2.14.2 802.1p-Based Priority.......................................................................................................................... 58 9.2.14.3 DiffServ-Based Priority........................................................................................................................ 58 9.3 MII Interface.................................................................................................................................................... 59 9.3.1 MII data interface ..................................................................................................................................... 59 9.3.2 MII Serial Management ............................................................................................................................ 59 9.3.3 Serial Management Interface ................................................................................................................... 60 9.3.4 Management Interface - Read Frame Structure ...................................................................................... 60 9.3.5 Management Interface - Write Frame Structure ...................................................................................... 60 9.4 Internal PHY functions .................................................................................................................................. 61 9.4.1 100Base-TX Operation ............................................................................................................................ 61 9.4.1.1 4B5B Encoder ....................................................................................................................................... 61 9.4.1.2 Scrambler .............................................................................................................................................. 61 9.4.1.3 Parallel to Serial Converter ................................................................................................................... 61 9.4.1.4 NRZ to NRZI Encoder ........................................................................................................................... 61 9.4.1.5 MLT-3 Converter ................................................................................................................................... 61 9.4.1.6 MLT-3 Driver ......................................................................................................................................... 61 9.4.1.7 4B5B Code Group................................................................................................................................. 62 9.4.2 100Base-TX Receiver .............................................................................................................................. 63 9.4.2.1 Signal Detect ......................................................................................................................................... 63 9.4.2.2 Adaptive Equalization............................................................................................................................ 63 9.4.2.3 MLT-3 to NRZI Decoder........................................................................................................................ 63 9.4.2.4 Clock Recovery Module ........................................................................................................................ 63 9.4.2.5 NRZI to NRZ ......................................................................................................................................... 63 9.4.2.6 Serial to Parallel .................................................................................................................................... 63 9.4.2.7 Descrambler .......................................................................................................................................... 63 9.4.2.8 Code Group Alignment.......................................................................................................................... 64 9.4.2.9 4B5B Decoder....................................................................................................................................... 64 9.4.3 10Base-T Operation................................................................................................................................. 64 9.4.4 Collision Detection ................................................................................................................................... 64 9.4.5 Carrier Sense ........................................................................................................................................... 64 8 Preliminary datasheet DM9013-15-DS-P03 April 9, 2009 DM9013 3-port switch with Processor Interface 9.4.6 Auto-Negotiation ...................................................................................................................................... 64 10. DC AND AC ELECTRICAL CHARACTERISTICS ..................................................... 65 10.1 Absolute Maximum Ratings ....................................................................................................................... 65 10.2 Operating Conditions.................................................................................................................................. 65 10.3 DC Electrical Characteristics ..................................................................................................................... 66 10.4 AC characteristics ....................................................................................................................................... 66 10.4.1 Power On Reset Timing ......................................................................................................................... 66 10.4.2 Processor I/O Read Timing.................................................................................................................... 67 10.4.3 Processor I/O Write Timing .................................................................................................................... 68 10.4.4 Port 2 MII Interface Transmit Timing...................................................................................................... 69 10.4.5 Port 2 MII Interface Receive Timing....................................................................................................... 69 10.4.6 MII Management Interface Timing ......................................................................................................... 70 10.4.7 EEPROM Timing.................................................................................................................................... 70 11. 12. 13. APPLICATION CIRCUIT ............................................................................................ 71 PACKAGE INFORMATION........................................................................................ 74 ORDERING INFORMATION ...................................................................................... 75 Preliminary datasheet DM9013-15-DS-P03 April 9, 2009 9 DM9013 3-port switch with Processor Interface 1. General Description The DM9013 is a fully integrated and cost-effective fast Ethernet switch controller with two ports 10M/100M PHY, one port MII or RMII or Reverse MII interface, and general processor bus interface. The controller provides basic Layer-2 switch functions and advanced IEEE 802.1Q VLAN and priority queuing scheme. The integrated two ports PHY are compliant with IEEE 802.3u standards. The MII interface provides the flexibility to connect Ethernet PHY or SoC with MII/RMII interface. The DM9013 provides direct interface to the general processor bus with 8-, 16-, or 32-bit data to access internal memory. 2. Block Diagram Switch Engine Port 0 MDI / MDIX 10/100M PHY 10/100M MAC Switch Fabric Embedded Memory Memory BIST Port 1 MDI / MDIX 10/100M PHY 10/100M MAC Switch Controller Memory Management Port 2 MII / RMII Reverse MII 10/100M MAC LED Control Processor Interface Host MAC Control Registers MIB Counters EEPROM Interface Bandwidth LEDs 8 , 16 , 32 bit Processor Bus EEPROM 10 Preliminary datasheet DM9013-15-DS-P03 April 9, 2009 DM9013 3-port switch with Processor Interface 3. Features Ethernet Switch with two 10/100Mb PHY, one MII/RMII, and general processor bus interface Support Reverse-MII Processor bus slave architecture EEPROM interface for power up configurations Support TCP/UDP/IPv4 checksum offload Support HP Auto-MDIX Support IEEE 802.3x Flow Control in Full-duplex mode Support Back Pressure Flow Control in Half-duplex mode Per port support 4 priority queues by Port-based, 802.1P VLAN, and IP TOS priority Support 802.1Q VLAN up-to 16 VLAN group Support VLAN ID tag/untag options Per port support bandwidth, ingress and egress rate control Support Broadcast Storming filter function Support Store and Forward switching approach Support up-to 1K Uni-cast MAC addresses Automatic aging scheme Support MIB counters for diagnostic uP data bus driving capability adjustable Port 2 TXD/TXE driving capability adjustable Auto. control to prevent memory read count error 128-pin LQFP 1.8V internal core, 3.3V I/O with 5V tolerant Preliminary datasheet DM9013-15-DS-P03 April 9, 2009 11 DM9013 3-port switch with Processor Interface 4. Pin Configuration : 128 pin LQFP BGRESG RXD2_1 RXD2_2 RXD2_3 RXD2_0 BGRES AVDD3 AVDD3 RXDV2 RXER2 TEST3 TEST2 AGND AGND AVDDI TEST1 AVDDI AGND AGND VCC3 RX0+ 95 94 91 90 89 81 88 86 84 80 78 73 69 68 67 66 93 92 85 83 96 87 82 79 77 76 75 74 72 71 VCNTL VREF AVDD3 VCC3 X1 X2 GND LNK1_LED SPD1_LED FDX1_LED LNK0_LED SPD0_LED FDX0_LED WOL GP6 GP5 GP4 GP3 GP2 SCLK GP1 GP0 BWLED0 VCCI BWLED1 BWLED2 BWLED3 BWLED4 GND BWLED5 BWLED6 BWLED7 70 65 CRS2 RXC2 COL2 RX1+ RX0- TX0TX0+ TX1+ RX1- TX1- GND 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 25 30 28 10 11 12 13 14 15 16 19 23 17 18 20 21 22 24 26 27 3 4 29 1 2 5 6 7 8 9 31 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 TXC2 TXE2 VCC3 TXD2_0 TXD2_1 TXD2_2 TXD2_3 VCCI MDIO MDC GND PWRST# EECS EECK EEDO EEDI VCC3 SD31 SD30 GND SD29 SD28 SD27 SD26 VCC3 SD25 SD24 SD23 SD22 GND SD21 SD20 DM9013 CMD CS# SD4 SD0 SD1 SD3 SD5 SD6 SD7 SD2 SD8 SD9 VCCI SD14 VCC3 VCC3 12 VCC3 SD10 SD15 SD17 SD18 SD11 SD13 SD12 IOW# SD16 SD19 IRQ GND GND IOR# GND Preliminary datasheet DM9013-15-DS-P03 April 9, 2009 DM9013 3-port switch with Processor Interface 5. Pin Description I = Input, O = Output, I/O = Input / Output, O/D = Open Drain, P = Power, PD=internal pull-low (about 50K Ohm) # = asserted Low 5.1 Processor Bus Interface Pin No. 1 Pin Name CMD I/O I Description Command Type When high, the access of this command cycle is DATA port When low, the access of this command cycle is INDEX port Processor Chip select Command Processor Write Command Processor Read Command Interrupt Request Processor Data Bus bit 0~15 Processor Data Bus bit 16~31 or General purpose pins when data bus is in 16-bit mode Reserved 2 3 5 6 7,8,9,10,12,13,14,15, 16,17,19,20,22,23,25,26 28,29,30,31,33,34,36,37, 38,39,41,42,43,44,46,47 110 CS# IOW# IOR# IRQ SD0~15 SD16~31 Reserved I I I O I/O I/O O 5.2 General and LED pins Pin No. 118,117,115,114, 113,112,111 119,121,122,123, 124,126,127,128 Pin Name GP0~6 BWLED0~7 I/O I/O I/O Description General I/O Ports Registers GPCR and GPR can program these pins Bandwidth LED 5.3 P2 MII / RMII / Reverse MII Interfaces 5.3.1 MII Interfaces Pin No. 55 356 58,59,60,61 63 64 65 66 67 Preliminary datasheet DM9013-15-DS-P03 April 9, 2009 Pin Name MDC MDIO TXD2_3~0 TXE2 TXC2 CRS2 COL2 RXER2 I/O O,PD I/O O,PD O,PD I/O I/O I/O I Description MII Serial Management Data Clock MII Serial Management Data Port 2 MII Transmit Data 4-bit nibble data outputs (synchronous to the TXC2) Port 2 MII Transmit Enable Port 2 MII Transmit Clock. Port 2 MII Carrier Sense Port 2 MII Collision Detect. Port 2 MII Receive Error 13 DM9013 3-port switch with Processor Interface 68 70 71,72,73,74 RXC2 RXDV2 RXD2_3~0 I I I Port 2 MII Receive Clock Port 2 MII Receive Data Valid Port 2 MII Receive Data 4-bit nibble data input (synchronous to RXC2) 5.3.2 RMII Interfaces Pin No. 55 56 58,59 60,61 63 64 65 66 67 68 70 71,72 73,74 Pin Name MDC MDIO TXD2_3~2 TXD2_1~0 TXE2 TXC2 CRS2 COL2 RXER2 RXC2 RXDV2 RXD2_3~2 RXD2_1~0 I/O O,PD I/O O,PD O,PD O,PD O I I I I I I I Description MII Serial Management Data Clock MII Serial Management Data Reserved RMII Transmit Data RMII Transmit Enable. Reserved RMII CRS_DV Reserved, tie to ground in application. Reserved, tie to ground in application. 50MHz reference clock. Reserved, tie to ground in application. Reserved, tie to ground in application. RMII Receive Data. 5.3.3 Reverse MII Interfaces Pin No. Pin Name 55 56 58,59,60,61 63 64 65 66 67 68 70 71,72,73,74 MDC MDIO TXD2_3~0 TXE2 TXC2 CRS2 COL2 RXER2 RXC2 RXDV2 RXD2_3~0 I/O O,PD I/O O,PD O,PD O O O I I I I Description Reserved Reserved Port 2 MII Transmit Data 4-bit nibble data outputs (synchronous to the TXC2) Port 2 MII Transmit Enable 25MHz clock output Port 2 carrier sense output when TXE2 or RXDV2 asserted. Port 2 collision output when TXE2 and RXDV2 asserted. Port 2 MII Receive Error Port 2 MII Receive Clock Port 2 MII Receive Data Valid Port 2 MII Receive Data 4-bit nibble data input (synchronous to RXC2) 14 Preliminary datasheet DM9013-15-DS-P03 April 9, 2009 DM9013 3-port switch with Processor Interface 5.4 EEPROM Interfaces Pin No. 49 50 Pin Name EEDI EEDO I/O I,PD O,PD Description EEPROM Data In EEPROM Data Out This pin is used serially to write op-codes, addresses and data into the EEPROM. EEPROM Serial Clock This pin is used as the clock for the EEPROM data transfer. EEPROM Chip Selection. 51 52 5.5 LED Pins Pin No. 104 EECK EECS O,PD O,PD Pin Name LNK1_LED I/O O Description Port 1 Link / Active LED It is the combined LED of link and carrier sense signal of the internal PHY1 Port 1 Speed LED Its low output indicates that the internal PHY1 is operated in 100M/S, or it is floating for the 10M mode of the internal PHY1 Port 1 Full-duplex LED Its low output indicates that the internal PHY1 is operated in full-duplex mode, or it is floating for the half-duplex mode of the internal PHY1 Port 0 Link / Active LED It is the combined LED of link and carrier sense signal of the internal PHY0 Port 0 Speed LED Its low output indicates that the internal PHY0 is operated in 100M/S, or it is floating for the 10M mode of the internal PHY0 Port 0 Full-duplex LED Its low output indicates that the internal PHY0 is operated in full-duplex mode, or it is floating for the half-duplex mode of the internal PHY0 105 SPD1_LED O 106 FDX1_LED O 107 LNK0_LED O 108 SPD0_LED O 109 FDX0_LED O Preliminary datasheet DM9013-15-DS-P03 April 9, 2009 15 DM9013 3-port switch with Processor Interface 5.6 Clock Interface Pin No. 101 102 116 5.7 Network Interface Pin No. 80,81 84,85 88,89 92,93 95 96 97 98 5.8 Miscellaneous Pins Pin No. 53 76 77 Pin Name X1 X2 SCLK I/O I O I Description Crystal 25MHz In Crystal 25MHz Out External system clock source Pin Name TX1+/RX1+/TX0+/RX0+/BGRES BGGND VCNTL VREF I/O I/O I/O I/O I/O I/O P I/O O Port 1 TP TX Port 1 TP RX Port 0 TP TX Port 0 TP RX Band gap Pin Band gap Ground 1.8V Voltage control Voltage Reference Description Pin Name PWRST# TEST1 TEST2 I/O Description 78 5.9 Power Pins Pin No. 4,18,32,40,48,62,75,100 24,57,120 11,21,27,35,45, 54,69,103,125 86,94,99 79,87 82,83,90,91 TEST3 I Power on Reset. I,PD Tie to ground in application I,PD 0: 3-port mode All ports are active in this mode. 1: 2-port mode Only 2 ports are active in this mode. Port 1 or port 2 can be disabled by strap TXEN2. In this mode, the disabled port's memory resource is shared by processor port and the other 2 ports. I,PD Tie to ground in application Pin Name VCC3 VCCI GND AVDD3 AVDDI AGND I/O P P P P P P Description Digital 3.3V Internal 1.8V core power Digital GND Analog 3.3V power Analog 1.8V power Analog GND 16 Preliminary datasheet DM9013-15-DS-P03 April 9, 2009 DM9013 3-port switch with Processor Interface 5.10 Strap Pins Table 1: pull-high 1K~10K, 0: default floating. 5.10.1 Strap pin in 3-port mode Pin No. Pin Name Description 50, 51 EECK EEDO 52 55 58 59 EECS MDC TXD2_3 TXD2_2 60,61 TXD2_1,0 63 TXEN2 Processor Data Bus Width EECK EEDO data width 0 0 16-bit 0 1 32-bit 1 0 8-bit 1 1 reserved 0: use internal system clock 1: use SCLK as system clock Polarity of IRQ 0: IRQ pin high active 1: IRQ pin low active; ISA pin control 0: GP6/5 as normal general purpose pins 1: GP6 as IO16, GP5 as IOWAIT used in ISA bus only Port 2 in force mode GP4 : 0 strap as link status, : 1 strap as not link status, GP3 : 0 strap as full-duplex status, : 1 strap as half-duplex status, GP2 : 0 strap as speed100 status, : 1 strap as speed10 status. 00: P2 is MII mode (Default) 01: P2 is in reverse MII mode 10: P2 is in RMII mode 11: reserved Output Type of IRQ 0: IRQ pin is force output 1: IRQ pin is Open-Collect Preliminary datasheet DM9013-15-DS-P03 April 9, 2009 17 DM9013 3-port switch with Processor Interface 5.10.2 Strap pin in 2-port mode Pin No. Pin Name Description 50, 51 EECK EEDO DATA Bus Width EECK EEDO data width 0 0 16-bit 0 1 32-bit 1 0 8-bit 1 1 reserved 0: use internal system clock 1: use SCLK as system clock Polarity of IRQ 0: IRQ pin high active 1: IRQ pin low active; ISA pin control 0: GP6/5 as normal general purpose pins 1: GP6 as IO16, GP5 as IOWAIT used in ISA bus only Port 2 in force mode GP4 : 0 strap as link status, : 1 strap as not link status, GP3 : 0 strap as full-duplex status, : 1 strap as half-duplex status, GP2 : 0 strap as speed100 status, : 1 strap as speed10 status. TXD2_1 TXD2_0 Port 2 mode 0 0 P2 is MII mode (Default) 0 1 P2 is in reverse MII mode 1 0 P2 is in RMII mode 1 1 reserved 0: port 2 disabled 1: port 1 disabled 52 55 EECS MDC 58 59 TXD2_3 TXD2_2 60,61 TXD2_1,0 63 TXEN2 18 Preliminary datasheet DM9013-15-DS-P03 April 9, 2009 DM9013 3-port switch with Processor Interface 6. Control and Status Register Set The DM9013 implements several control and status registers, which can be accessed by the host. These CSRs Register Description NCR NSR TCR RCR RSR ROCR FCR EPCR EPAR EPDRL EPDRH PAR MAR GPCR GPR RXPLLR RXPLHR RASR RACR VID PID CHIPR TCR2 TCSCR RCSCSR GPCR2 GPR2 GPCR3 GPR3 DRIVER IRQCR P2FRV TXBSCR MONIR1 MONIR2 MONIR3 SWITCHCR VLANCR SWITCHSR BWLED P_INDEX Preliminary datasheet DM9013-15-DS-P03 April 9, 2009 are byte aligned. All CSRs are set to their default values by hardware or software reset unless specified Offset Default value after reset Network Control Register 00H 00H Network Status Register 01H 00H TX Control Register 02H 00H RX Control Register 05H 00H RX Status Register 06H 00H Receive Overflow Counter Register 07H 00H Flow Control Register 0AH 00H EEPROM & PHY Control Register 0BH 00H EEPROM & PHY Address Register 0CH 40H EEPROM & PHY Low Byte Data Register 0DH XXH EEPROM & PHY High Byte Data Register 0EH XXH Processor Port Physical Address Registers 10H-15H by EEPROM Processor Port Multicast Address Registers 16H-1DH XXH General Purpose Control Register 1EH 01H General Purpose Register 1FH XXH RX Packet Length Low Register 20H 00H RX Packet Length High Register 21H 00H RX Additional Status Register 26H 00H RX Additional Control Register 27H 00H Vendor ID 28H-29H 0A46H Product ID 2AH-2BH 9013H CHIP Revision 2CH 01H TX Control Register 2 2DH 00H Transmit Check Sum Control Register 31H 00H Receive Check Sum Control Status Register 32H 00H General Purpose Control Register 2 34H 00H General Purpose Register 2 35H 00H General Purpose Control Register 3 36H 00H General Purpose Register 3 37H 00H uP Data Bus driving capability Register 38H 21H IRQ Control Register 39H 00H Port 2 driving capability Register 3AH 21H TX Block Size Control Register 3FH 20H Monitor Register 1 40H XXH Monitor Register 2 41H XXH Monitor Register 3 42H XXH SWITCH Control Register 52H 00H VLAN Control Register 53H 00H SWITCH Status Register 54H 00H Bandwidth LED Control Register 55H FFH Per Port Control/Status Index Register 60H 00H 19 DM9013 3-port switch with Processor Interface P_CTRL P_STUS P_RATE P_BW P_UNICAST P_MULTI P_BCAST P_UNKNWN P_PRI VLAN_TAGL VLAN_TAGH P_MIB_IDX MIB_DAT MIB_DAT MIB_DAT MIB_DAT PVLAN TOS_MAP VLAN_MAP MRCMDX MRCMD MRRL MRRH MWCMDX MWCMD Per Port Control Data Register Per Port Status Data Register Per Port Ingress and Egress Rate Control Register Bandwidth Control Register Per Port Block Unicast ports Control Register Per Port Block Multicast ports Control Register Per Port Block Broadcast ports Control Register Per Port Block Unknown ports Control Register Per Port Priority Queue Control Register Per Port VLAN Tag Low Byte Register Per Port VLAN Tag High Byte Register Per Port MIB counter Index Register MIB counter Data Register bit 0~7 MIB counter Data Register bit 8~15 MIB counter Data Register bit 16~23 MIB counter Data Register bit 24~31 Port-based VLAN mapping table registers TOS Priority Map Register VLAN priority Map Register Memory Data Pre-Fetch Read Command Without Address Increment Register Memory Data Read Command With Address Increment Register Memory Data Read address Register Low Byte Memory Data Read address Register High Byte Memory Data Write Command Without Address Increment Register Memory Data Write Command With Address Increment Register Memory Data Write address Register Low Byte Memory Data Write address Register High Byte TX Packet Length Low Byte Register TX Packet Length High Byte Register Interrupt Status Register Interrupt Mask Register 61H 62H 66H 67H 68H 69H 6AH 6BH 6DH 6EH 6FH 80H 81H 82H 83H 84H B0-BFH C0-CFH D0-D1H F0H F2H F4H F5H F6H F8H FAH FBH FCH FDH FEH FFH 00H 00H 00H 00H 00H 00H 00H 00H 00H 01H 00H 00H 00H 00H 00H 00H 0FH 00H~FFH 50H,FAH XXH XXH 00H 00H XXH XXH 00H 00H XXH XXH 00H 00H MWRL MWRH TXPLL TXPLH ISR IMR Key to Default In the register description that follows, the default column takes the form: E = default value from EEPROM T = default value from strap pin 20 Preliminary datasheet DM9013-15-DS-P03 April 9, 2009 DM9013 3-port switch with Processor Interface 6.1 Network Control Register (00H) Bit Name Default Description 7 RESERVED 0,RO Reserved 6 RESERVED P0,WO Reserved 5 CLR1 PH0,RW 0: REG. 01H auto-cleared after read 1: REG. 01H cleared by writing 1 to respected bit. 4:2 RESERVED 0,RO Reserved 1 LBK PH0, Loopback test Mode RW 0 RST PH0,RW Software reset and auto clear after 10us 6.2 Network Status Register (01H) Bit Name Default Description 7:6 RESERVED 0,RO Reserved 5 RESERVED PH0, Reserved RESERVED 0,RO Reserved 4 3 TX2END PHS0, TX Packet 2 Complete Status. RW/C1 This bit is set after transmit completion of packet index 2 If bit 5 of NCR is set, this bit is cleared by write 1; Otherwise it can be cleared by read or write 1. 2 TX1END PHS0, TX Packet 1 Complete status. RW/C1 This bit is set after transmit completion of packet index 1 If bit 5 of NCR is set, this bit is cleared by write 1; Otherwise it can be cleared by read or write 1. 1:0 RESERVED 0,RO Reserved 6.3 TX Control Register (02H) Bit Name Default 7:4 RESERVED 0,RO 3 CRC_DIS2 PHS0,RW 2 RESERVED 0,RO 1 CRC_DIS1 PHS0,RW 0 TXREQ PHS0,RW 6.4 RX Control Register (05H) Bit Name Default 7 HASHALL PHS0,RW RESERVED PHS0,RW 6 5 RESERVED PHS0,RW 4 RESERVED PHS0,RW 3 ALL PHS0,RW 2 RESERVED PHS0,RW 1 PRMSC PHS0,RW 0 RXEN PHS0,RW Description Reserved CRC Appends Disable for Packet Index 2 Reserved CRC Appends Disable for Packet Index 1 TX Request. Auto clears after transmit completely Description Filter All address in Hash Table Reserved Reserved Reserved Pass All Multicast Packets Reserved Promiscuous Mode RX Enable Preliminary datasheet DM9013-15-DS-P03 April 9, 2009 21 DM9013 3-port switch with Processor Interface 6.5 RX Status Register (06H) Bit Name Default 7:4 RESERVED 0,RO 3:2 SRCP 0,RO 1 CE PH0,RO 0 RESERVED 0,RO Description Reserved Source Port Number CRC Error It is set to indicate that the received frame ends with a CRC error Reserved 6.6 Receive Overflow Counter Register (07H) Bit Name Default Description 7 RXFU PHS0,R/C Receive Overflow Counter Overflow This bit is set when the ROC has an overflow condition 6:0 ROC PHS0,R/C Receive Overflow Counter This is a statistic counter to indicate the received packet count upon FIFO overflow 6.7 Flow Control Register (0AH) Bit Name Default 7:6 RESERVED 0,RO 5 4:0 FLOW_EN RESERVED PHS0,RW 0,RO Description Reserved RX Flow Control Enable Enables the pause packet for high/low water threshold control Reserved 6.8 EEPROM & PHY Control Register (0BH) Bit Name Default Description 7:6 RESERVED 0,RO Reserved 5 REEP PH0,RW Reload EEPROM. Driver needs to clear it up after the operation completes 4 WEP PH0,RW Write EEPROM Enable 3 EPOS PH0,RW EEPROM or PHY Operation Select When reset, select EEPROM; when set, select PHY 2 ERPRR PH0,RW EEPROM Read or PHY Register Read Command. Driver needs to clear it up after the operation completes. 1 ERPRW PH0,RW EEPROM Write or PHY Register Write Command. Driver needs to clear it up after the operation completes. 0 ERRE PH0,RO EEPROM Access Status or PHY Access Status When set, it indicates that the EEPROM or PHY access is in progress 6.9 EEPROM & PHY Address Register (0CH) Bit Name Default Description 7:6 PHY_ADR PH01,RW PHY Address bit 1 and 0; the PHY address bit [4:2] is force to 0. 5:0 EROA PH0,RW EEPROM Word Address or PHY Register Address 6.10 EPROM & PHY Data Register (0DH~0EH) Bit Name Default Description 7:0 EE_PHY_L PH0,RW EEPROM or PHY Low Byte Data (0DH) This data is made to write low byte of word address defined in Reg. CH to EEPROM or PHY 7:0 EE_PHY_H PH0,RW EEPROM or PHY High Byte Data (0EH) This data is made to write high byte of word address defined in Reg. CH to EEPROM or PHY 22 Preliminary datasheet DM9013-15-DS-P03 April 9, 2009 DM9013 3-port switch with Processor Interface 6.11 Physical Address Register (10H~15H) Bit Name Default 7:0 PAB5 E,RW Physical Address Byte 5 7:0 PAB4 E,RW Physical Address Byte 4 7:0 PAB3 E,RW Physical Address Byte 3 7:0 PAB2 E,RW Physical Address Byte 2 7:0 PAB1 E,RW Physical Address Byte 1 7:0 PAB0 E,RW Physical Address Byte 0 6.12 Multicast Address Register (16H~1DH) Bit Name Default 7:0 MAB7 X,RW Multicast Address Byte 7 7:0 MAB6 X,RW Multicast Address Byte 6 7:0 MAB5 X,RW Multicast Address Byte 5 7:0 MAB4 X,RW Multicast Address Byte 4 7:0 MAB3 X,RW Multicast Address Byte 3 7:0 MAB2 X,RW Multicast Address Byte 2 7:0 MAB1 X,RW Multicast Address Byte 1 7:0 MAB0 X,RW Multicast Address Byte 0 Description (15H) (14H) (13H) (12H) (11H) (10H) Description (1DH) (1CH) (1BH) (1AH) (19H) (18H) (17H) (16H) 6.13 General Purpose Control Register (1EH) Bit Name Default Description 7 RESERVED 0,RO Reserved 6:0 GPC PH,0,RW General Purpose Control 6~0 Define the input/output direction of pins GP6~0 respectively. 1: output, 0:input 6.14 General Purpose Register (1FH) Bit Name Default Description 7 RESERVED 0,RO Reserved 6:0 GEPIO X,RW General Purpose Data 6~0 These bits are reflect to pin GP6~0 respectively. 6.15 RX Packet Length Low Register ( 20H ) Bit Name Default 7:0 RXPLL PH,RO RX Packet Length Low byte Description 6.16 RX Packet Length High Register ( 21H ) Bit Name Default 7:0 RXPLH PH,RO RX Packet Length High byte Description Preliminary datasheet DM9013-15-DS-P03 April 9, 2009 23 DM9013 3-port switch with Processor Interface 6.17 RX Additional Status Register ( 26H ) Bit Name Default Description 7:4 RESERVED 0,RO Reserved 1:0 uP received pointer status, only available when RX pointer restriction is enabled ( Reg27h.7=0). RPTRS PH,RO 00: Within buffer 01: End of buffer 1x: Exceed buffer 6.18 RX Additional Control Register ( 27H ) Bit Name Default RPRD PHS0,RW RX pointer restriction disable 7 6:0 RESERVED 0,RO Reserved 6.19 Vendor ID Register (28H~29H) Bit Name Default 7:0 VIDH PE,0AH,RO Vendor ID High Byte (29H) 7:0 VIDL PE,46H.RO Vendor ID Low Byte (28H) 6.20 Product ID Register (2AH~2BH) Bit Name Default 7:0 PIDH PE,90H,RO Product ID High Byte (2BH) 7:0 PIDL PE,13H.RO Product ID Low Byte (2AH) 6.21 Chip Revision Register (2CH) Bit Name Default 7:0 CHIPR P01H,RO CHIP Revision Description Description Description Description 6.22 Transmit Control Register 2 (2DH) Bit Name Default Description 7 RESERVED 0,RW Reserved, Clear to 0 in application. 6:5 RESERVED 0,RO Reserved 4 ONEPM P0,RW One Packet Mode When set, only one packet transmit command can be issued before transmit completed. When cleared, at most two packet transmit command can be issued before transmit completed. 3:0 RESERVED 0,RO Reserved 6.23 Transmit Check Sum Control Register (31H) Bit Name Default Description 7~3 RESERVED 0,RO Reserved 2 UDPCSE HP0,RW UDP Checksum Generation Enable 1 TCPCSE HP0,RW TCP Checksum Generation Enable 0 IPCSE HP0,RW IP Checksum Generation Enable 24 Preliminary datasheet DM9013-15-DS-P03 April 9, 2009 DM9013 3-port switch with Processor Interface 6.24 Receive Check Sum Control Status Register (32H) Bit Name Default Description 7 UDPS HP0,RO UDP Checksum Status 1: if UDP packet checksum fail 6 TCPS HP0,RO TCP Checksum Status 1: if TCP packet checksum fail 5 IPS HP0,RO IP Checksum Status 1: if IP packet checksum fail 4 UDPP HP0,RO This is a UDP Packet 3 TCPP HP0,RO This is a TCP Packet 2 IPP HP0,RO This is a IP Packet 1 RCSEN HPS0,RW Receive Checksum Checking Enable When set, the checksum status will store in packet first byte of status header. 0 DCSE HPS0,RW Discard Checksum Error Packet When set, if IP/TCP/UDP checksum field is error, this packet will be discarded. 6.25 General Purpose Control Register 2 (34H) Bit Name Default Description 7~0 GPC2 HP0,RW General Purpose Control 2 Define the input/output direction of pins SD23~16, which are used as general purpose pins when none 32-bit mode and external MII mode, respectively. 6.26 General Purpose Register 2 (35H) Bit Name Default Description 7~0 GPD2 HP0,RW General Purpose Register 2 Data When the correspondent bit of General Purpose Control Register 2 is set, the value of the bit is reflected to pin SD23~16 When the correspondent bit of General Purpose Control Register 2 is 0, the value of the bit to be read is reflected from correspondent pins SD23~16 6.27 General Purpose Control Register 3 (36H) Bit Name Default Description 7~0 GPC3 HP0,RW General Purpose Control 3 Define the input/output direction of pins SD31~24, which are used as general purpose pins when none 32-bit mode and external MII mode, respectively. 6.28 General Purpose Register 3 (37H) Bit Name Default Description 7~0 GPD3 HP0,RW General Purpose Register 3 Data When the correspondent bit of General Purpose Control Register 3 is set, the value of the bit is reflected to pin SD31~24 When the correspondent bit of General Purpose Control Register 3 is 0, the value of the bit to be read is reflected from correspondent pins SD31~24 Preliminary datasheet DM9013-15-DS-P03 April 9, 2009 25 DM9013 3-port switch with Processor Interface 6.29 Processor Data Bus driving capability Register (38H) Bit Name Default RESERVED 0,RW reserved Description 7 6:5 ISA_CURR 4:3 2 1 0 Reserved STEP IOW_SPIKE IOR_SPIKE P01,RW P0,RW P0,RW P0,RW P1,RW SD Bus Current Driving/Sinking Capability 00: 2mA 01: 4mA (default) 10: 6mA 11: 8mA Reserved Data Bus Output stepping 1: disabled 0: enabled Eliminate IOW spike 1: eliminate about 2ns IOW spike Eliminate IOR spike 1: eliminate about 2ns IOR spike 6.30 Port 2 driving capability Register (3AH) Bit Name Default Description 7 Reserved 0,RO Reserved Port 2 TXD/TXECurrent Driving/Sinking Capability 6:5 00: 2mA P2_CURR P01,RW 01: 4mA (default) 10: 6mA 11: 8mA 4:0 RESERVED P01,RW reserved 6.31 IRQ Pin Control Register (39H) Bit Name Default 7:2 Reserved PS0,RO Reserved IRQ Pin Output Type Control 1 IRQ_TYPE PET0,RW 0: IRQ direct output 1: IRQ Open-Collector output IRQ Pin Polarity Control 0 IRQ_POL PET0,RW 0: IRQ active high 1: IRQ active low Description 6.32 TX Block Size Control Register (3FH) Bit Name Default Description 7:6 Reserved PS0,RO Reserved TX Block Size in 2-Port Mode This value defines the transmit block size in 256-byte unit. TX memory size = TX_SIZE * 256 bytes 5:0 TX_SIZE P20h,RW And then RX memory size = 16KB - (TX_SIZE + 1)*256-Byte Note: The value of TX_SIZE should be between 14H and 30H 26 Preliminary datasheet DM9013-15-DS-P03 April 9, 2009 DM9013 3-port switch with Processor Interface 6.33 Monitor Register 1 (40H) Bit Name Default 7 BWIDTH T0,RO 6 DWIDTH T0,RO 5 IRQOC ET0,RO 4 IRQP ET0,RO 3 IO16OC E0,RO 2 IO16P E0,RO 1:0 RESERVED 0,RO 6.34 Monitor Register 2 (41H) Bit Name Default 7 TEST3 RO 6 TEST2 RO 5 TEST1 RO 4 MDC T0,RO 3 EECS T0,RO 2 EECK T0,RO 1 EEDO T0,RO 0 EEDI T0,RO 6.35 Monitor Register 3 (42H) Bit Name Default 7:4 RESERVED 0,RO 4 TXE2 T0,RO 3 TXD2_3 T0,RO 2 TXD2_2 T0,RO 1 TXD2_1 T0,RO 0 TXD2_0 T0,RO 6.36 Monitor Register 4 (43H) Bit Name Default 7 RESERVED 0,RO 6:0 GPIO T0,RO Description 8-bit Data Strap Latch Status 32-bit Data Strap Latch Status IRQ Open-Collect Pin Status IRQ Polarity Pin Status IO16 Open-Collect Pin Status IO16 Polarity Pin Status Reserved Description TEST3 pin TEST2 pin TEST1 pin MDC Strap Status EECS Strap Status EECK Strap Status EEDO Strap Status EEDI Strap Status Description Reserved TXE2 Strap Status TXD2_3 Strap Status TXD2_2 Strap Status TXD2_1 Strap Status TXD2_0 Strap Status Description Reserved GPIO 0~6 Strap Status 6.37 Switch Control Register (52H) Bit Name Default Description 7 MEM_BIST PH0,RO Address Memory Test BIST Status 0: OK 1: Fail 6 RST_SW P0,RW Reset Switch Core and auto clear after 10us 5 RST_ANLG P0,RW Reset Analog PHY Core and auto clear after 10us 4:3 SNF_PORT PE00,RW Sniffer Port Number 2 CRC_DIS PE0,RW CRC checking disable 1:0 AGE PE0,RW Aging 00: no aging 01: 64sec+/- 32sec 10: 128sec+/- 64sec 11: 256sec+/- 128sec Preliminary datasheet DM9013-15-DS-P03 April 9, 2009 27 DM9013 3-port switch with Processor Interface 6.38 VLAN Control Register (53H) Bit Name Default Description 7 TOS6 PE0,RW Full ToS Using Enable 0: check most significant 3-bit only of TOS 1: check most significant 6-bit of TOS 6 RESERVED 0,RO Reserved 5 UNICAST PE0,RW Unicast packet can across VLAN boundary 4 VIDFF PE0,RW Replace VIDFF 3 VID1 PE0,RW Replace VID01 2 VID0 PE0,RW Replace VID0 1 PRI PE0,RW Replace priority field in the tag 0 VLAN PE0,RW VLAN mode enable 0: port-base VLAN 1: 802.1Q base VLAN mode enable 6.39 Switch Status Register (54H) Bit Name Default Description 7 MEM_BIST PH0,RO Address Memory Test BIST Status 0: OK 1: Fail 6:0 RESERVED 0,RO Reserved 6.40 Bandwidth LED Control Register (55H) Bit Name Default Description 7,6 RESERVED PH0,RW Reserved 5 P2_TX PH1,RW Port 2 transmit as event of bandwidth LED source 4 P2_RX PH0,RW Port 2 receive as event of bandwidth LED source 3 P1_TX PH1,RW Port 1 transmit as event of bandwidth LED source 2 P1_RX PH0,RW Port 1 receive as event of bandwidth LED source 1 P0_TX PH1,RW Port 0 transmit as event of bandwidth LED source 0 P0_RX PH0,RW Port 0 receive as event of bandwidth LED source 6.41 Per Port Control/Status Index Register (60H) Bit Name Default Description 7:5 reserved PHS0,RW reserved 4:2 reserved 0,RO reserved 1:0 INDEX PHS0,RW Port index for register 61h~84h Write the port number to this register before write/read register 61h~84h. 6.42 Per Port Control Data Register (61H) Bit Name Default Description 7 RESERVED PE0,RW Reserved 6 PARTI_EN PE0,RW Enable Partition Detection 5 NO_DIS_RX PE0,RW Not Discard RX Packets when Ingress Bandwidth Control 28 Preliminary datasheet DM9013-15-DS-P03 April 9, 2009 DM9013 3-port switch with Processor Interface 4 FLOW_DIS PE0,RW Flow control in full duplex mode, or back pressure in half duplex mode enable 0 - enable 1 - disable Bandwidth Control 0: Control with Ingress and Egress separately, ref to Register 66h. 1: Control with Ingress or Egress, ref to Register 67h Broadcast packet filter 0 - accept broadcast packets 1 - reject broadcast packets Multicast packet filter 0 - accept multicast packets 1 - reject multicast packets Broadcast Storm Control 0 - only broadcast packet 1 - also multicast packet 3 BANDWIDTH PE0,RW 2 BP_DIS PE0,RW 1 MP_DIS PE0,RW 0 MP_STORM PE0,RW 6.43 Per Port Status Data Register (62H) Bit Name Default Description 7:6 RESERVED P0,RO Reserved 5 LP_FCS P0,RO Link Partner Flow Control Enable Status 4 BIST P0,RO BIST status 0: SRAM BIST pass 1: SRAM BIST fail 3 RESERVED 0,RO Reserved 2 SPEED2 P0,RO 0: 10Mbps, 1:100Mbps 1 FDX2 P0,RO 0: half-duplex, 1: full-duplex 0 LINK2 P0,RO 0: not Link status, 1: Link status 6.44 Per Port Forward Control Register (65H) Bit Name Default Description 7 LOOPBACK PH0,RW Loop-back mode 6 MONI_TX PH0,RW TX Packet Monitored 5 MONI_RX PH0,RW RX Packet Monitored 4 DIS_BMP PH0,RW Broad/Multicast packet do not monitored 3 Reserved PH0,RW Reserved 2 TX_DIS PH0,RW Packet Transmit disabled 1 RX_DIS PH0,RW Packet receive disabled 0 ADR_DIS PH0,RW Address learning disabled Preliminary datasheet DM9013-15-DS-P03 April 9, 2009 29 DM9013 3-port switch with Processor Interface 6.45 Per Port Ingress/Egress Control Register (66H) Bit Name Default 7:4 INGRESS PE0,RW Ingress Rate Control 0000: none 0001: 64K 0010: 128K 0011: 256K 0100: 512K 0101: 1M 0110: 2M 0111: 4M 1000: 8M 1001: 16M 1010: 32M 1011: 48M 1100: 64M 1101: 72M 1110: 80M 1111: 88M 3:0 EGRESS PE0,RW Egress Rate Control 0000: none 0001: 64K 0010: 128K 0011: 256K 0100: 512K 0101: 1M 0110: 2M 0111: 4M 1000: 8M 1001: 16M 1010: 32M 1011: 48M 1100: 64M 1101: 72M 1110: 80M 1111: 88M Description 30 Preliminary datasheet DM9013-15-DS-P03 April 9, 2009 DM9013 3-port switch with Processor Interface 6.46 Bandwidth Control Setting Register (67H) Bit Name Default Description 7:4 BSTH PE0,RW Broadcast Storm Threshold 0000: no broadcast storm control 0001: 8K packets/sec 0010: 16K packets/sec 0011: 64K packets/sec 0100: 5% 0101: 10% 0110: 20% 0111: 30% 1000: 40% 1001: 50% 1010: 60% 1011: 70% 1100: 80% 1101: 90% 111X: no broadcast storm control 3:0 BW CTRL PE0,RW Received packet length counted. Bandwidth table below. 0000: none 0001: 64K 0010: 128K 0011: 256K 0100: 512K 0101: 1M 0110: 2M 0111: 4M 1000: 8M 1001: 16M 1010: 32M 1011: 48M 1100: 64M 1101: 72M 1110: 80M 1111: 88M 6.47 Per Port Block Unicast ports Control Register (68H) Bit Name Default Description 7:4 RESERVED PH0,RW Reserved 3:0 BLK_UP PH0,RW Ports of unicast packet be blocked 6.48 Per Port Block Multicast ports Control Register (69H) Bit Name Default Description 7:4 RESERVED PH0,RW Reserved 3:0 BLK_MP PH0,RW Ports of multicast packet be blocked 6.49 Per Port Block Broadcast ports Control Register (6AH) Bit Name Default Description 7:4 RESERVED PH0,RW Reserved 3:0 BLK_BP PH0,RW Ports of broadcast packet be blocked Preliminary datasheet DM9013-15-DS-P03 April 9, 2009 31 DM9013 3-port switch with Processor Interface 6.50 Per Port Block Unknown ports Control Register (6BH) Bit Name Default Description 7:4 RESERVED PH0,RW Reserved 3:0 BLK_UKP PH0,RW Ports of unknown packet be blocked 6.51 Per Port Priority Queue Control Register (6DH) Bit Name Default Description 7 TAG_OUT PE0,RW Output Packet Tagging Enable 6 PRI_DIS PE0,RW Priority Queue Disable 5 WFQUE PE0,RW 8:4:2:1 0: queue 3 > 2 > 1 > 0 1: 8:4:2:1 4 TOS_PRI PE0,RW Priority ToS over VLAN 3 TOS_OFF PE0,RW ToS Priority Classification disable 2 PRI_OFF PE0,RW 802.1 p Priority Classification disable 1:0 P_PRI PE0,RW Port Base priority 00= queue 0, 01=queue 1, 10=queue 2, 11=queue 3 6.52 Per Port VLAN Tag Low Byte Register (6EH) Bit Name Default 7:0 VID70 PE01,RW VID[7:0] 6.53 Per Port VLAN Tag High Byte Register (6FH) Bit Name Default 7:5 PRI PE0,RW Tag [15:13] 4 CFI PE0,RW Tag[12] 3:0 VID118 PE0,RW VID[11:8] Description Description 6.54 MIB counter Port Index Register (80H) Bit Name Default Description 7 READY P0,RO MIB counter data is ready When this register is written with INDEX data, this bit is cleared and the MIB counter reading is in progress. After end of read MIB counter, the MIB data is loaded into register 81H~84H, and this bit is set to indicate that the MIB data is ready. 6:5 reserved 0,RO Reserved 4:0 INDEX PHS0,RW MIB counter index 0~9, each counter is 32-bit in Register 81h~84h. Write the MIB counter index to this register before read them. 6.55 MIB counter Data Register (81H~84H) Bit Name Default 81H Counter0 X,RO Counter's data bit 7~0 82H Counter1 X,RO Counter's data bit 15~8 83H Counter2 X,RO Counter's data bit 23~16 84H Counter3 X,RO Counter's data bit 31~24 Description 32 Preliminary datasheet DM9013-15-DS-P03 April 9, 2009 DM9013 3-port switch with Processor Interface MIB counter: RX Byte Counter Registers (00H) MIB counter: RX Uni-cast Packet Counter Registers (01H) MIB counter: RX Multi-cast Packet Counter Registers (02H) MIB counter: RX Discard Packet Counter Registers (03H) MIB counter: RX Error Packet Counter Registers (04H) MIB counter: TX Byte Counter Registers (05H) MIB counter: TX Uni-cast Packet Counter Registers (06H) MIB counter: TX Multi-cast Packet Counter Registers (07H) MIB counter: TX Discard Packet Counter Registers (08H) MIB counter: TX Error Packet Counter Registers (09H) 6.56 Port-based VLAN mapping table Registers (B0H~BFH) Bit Name Default 7:4 RESERVED PE0,RO Reserved 3:0 PORTS PEF,RW Port 3(uP) 2~0 6.57 TOS Priority Map Registers (C0H~CFH) C0H: Bit 7:6 5:4 3:2 1:0 C1H: Bit 7:6 5:4 3:2 1:0 C2H: Bit 7:6 5:4 3:2 1:0 Name TOSB TOSA TOS9 TOS8 Default PE0,RW PE0,RW PE0,RW PE0,RW Description If bit 53H.7 =1 :TOS[7:2]=0BH If bit 53H.7 =1 :TOS[7:2]=0AH If bit 53H.7 =1 :TOS[7:2]=09H If bit 53H.7 =1 :TOS[7:2]=08H Name TOS7 TOS6 TOS5 TOS4 Default PE0/3,RW PE0/3,RW PE0/2,RW PE0/2,RW Description If bit 53H.7 =1 :TOS[7:2]=07H, otherwise TOS]7:5]=07H If bit 53H.7 =1 :TOS[7:2]=06H, otherwise TOS]7:5]=06H If bit 53H.7 =1 :TOS[7:2]=05H, otherwise TOS]7:5]=05H If bit 53H.7 =1 :TOS[7:2]=04H, otherwise TOS]7:5]=04H Name TOS3 TOS2 TOS1 TOS0 Default PE0/1,RW PE0,/1RW PE0,RW PE0,RW Description If bit 53H.7 =1 :TOS[7:2]=03H, otherwise TOS]7:5]=03H If bit 53H.7 =1 :TOS[7:2]=02H, otherwise TOS]7:5]=02H If bit 53H.7 =1 :TOS[7:2]=01H, otherwise TOS]7:5]=01H If bit 53H.7 =1 :TOS[7:2]=00H, otherwise TOS]7:5]=00H Description Preliminary datasheet DM9013-15-DS-P03 April 9, 2009 33 DM9013 3-port switch with Processor Interface C3H: Bit 7:6 5:4 3:2 1:0 C4H: Bit 7:6 5:4 3:2 1:0 C5H: Bit 7:6 5:4 3:2 1:0 C6H: Bit 7:6 5:4 3:2 1:0 C7H: Bit 7:6 5:4 3:2 1:0 C8H: Bit 7:6 5:4 3:2 1:0 Name TOS23 TOS22 TOS21 TOS20 Default PE2,RW PE2,RW PE2,RW PE2,RW Description If bit 53H.7 =1 :TOS[7:2]=23H If bit 53H.7 =1 :TOS[7:2]=22H If bit 53H.7 =1 :TOS[7:2]=21H If bit 53H.7 =1 :TOS[7:2]=20H Name TOS1F TOS1E TOS1D TOS1C Default PE1,RW PE1,RW PE1,RW PE1,RW Description If bit 53H.7 =1 :TOS[7:2]=1FH If bit 53H.7 =1 :TOS[7:2]=1EH If bit 53H.7 =1 :TOS[7:2]=1DH If bit 53H.7 =1 :TOS[7:2]=1CH Name TOS1B TOS1A TOS19 TOS18 Default PE1,RW PE1,RW PE1,RW PE1,RW Description If bit 53H.7 =1 :TOS[7:2]=1BH If bit 53H.7 =1 :TOS[7:2]=1AH If bit 53H.7 =1 :TOS[7:2]=19H If bit 53H.7 =1 :TOS[7:2]=18H Name TOS17 TOS16 TOS15 TOS14 Default PE1,RW PE1,RW PE1,RW PE1,RW Description If bit 53H.7 =1 :TOS[7:2]=17H If bit 53H.7 =1 :TOS[7:2]=16H If bit 53H.7 =1 :TOS[7:2]=15H If bit 53H.7 =1 :TOS[7:2]=14H Name TOS13 TOS12 TOS11 TOS10 Default PE1,RW PE1,RW PE1,RW PE1,RW Description If bit 53H.7 =1 :TOS[7:2]=13H If bit 53H.7 =1 :TOS[7:2]=12H If bit 53H.7 =1 :TOS[7:2]=11H If bit 53H.7 =1 :TOS[7:2]=10H Name TOSF TOSE TOSD TOSC Default PE0,RW PE0,RW PE0,RW PE0,RW Description If bit 53H.7 =1 :TOS[7:2]=0FH If bit 53H.7 =1 :TOS[7:2]=0EH If bit 53H.7 =1 :TOS[7:2]=0DH If bit 53H.7 =1 :TOS[7:2]=0CH 34 Preliminary datasheet DM9013-15-DS-P03 April 9, 2009 DM9013 3-port switch with Processor Interface C9H: Bit 7:6 5:4 3:2 1:0 CAH: Bit 7:6 5:4 3:2 1:0 CBH: Bit 7:6 5:4 3:2 1:0 CCH: Bit 7:6 5:4 3:2 1:0 CDH: Bit 7:6 5:4 3:2 1:0 CEH: Bit 7:6 5:4 3:2 1:0 Name TOS3B TOS3A TOS39 TOS38 Default PE3,RW PE3,RW PE3,RW PE3,RW Description If bit 53H.7 =1 :TOS[7:2]=3BH If bit 53H.7 =1 :TOS[7:2]=3AH If bit 53H.7 =1 :TOS[7:2]=39H If bit 53H.7 =1 :TOS[7:2]=38H Name TOS37 TOS36 TOS35 TOS34 Default PE3,RW PE3,RW PE3,RW PE3,RW Description If bit 53H.7 =1 :TOS[7:2]=37H If bit 53H.7 =1 :TOS[7:2]=36H If bit 53H.7 =1 :TOS[7:2]=35H If bit 53H.7 =1 :TOS[7:2]=34H Name TOS33 TOS32 TOS31 TOS30 Default PE3,RW PE3,RW PE3,RW PE3,RW Description If bit 53H.7 =1 :TOS[7:2]=33H If bit 53H.7 =1 :TOS[7:2]=32H If bit 53H.7 =1 :TOS[7:2]=31H If bit 53H.7 =1 :TOS[7:2]=30H Name TOS2F TOS2E TOS2D TOS2C Default PE2,RW PE2,RW PE2,RW PE2,RW Description If bit 53H.7 =1 :TOS[7:2]=2FH If bit 53H.7 =1 :TOS[7:2]=2EH If bit 53H.7 =1 :TOS[7:2]=2DH If bit 53H.7 =1 :TOS[7:2]=2CH Name TOS2B TOS2A TOS29 TOS28 Default PE2,RW PE2,RW PE2,RW PE2,RW Description If bit 53H.7 =1 :TOS[7:2]=2BH If bit 53H.7 =1 :TOS[7:2]=2AH If bit 53H.7 =1 :TOS[7:2]=29H If bit 53H.7 =1 :TOS[7:2]=28H Name TOS27 TOS26 TOS25 TOS24 Default PE2,RW PE2,RW PE2,RW PE2,RW Description If bit 53H.7 =1 :TOS[7:2]=27H If bit 53H.7 =1 :TOS[7:2]=26H If bit 53H.7 =1 :TOS[7:2]=25H If bit 53H.7 =1 :TOS[7:2]=24H Preliminary datasheet DM9013-15-DS-P03 April 9, 2009 35 DM9013 3-port switch with Processor Interface CFH: Bit 7:6 5:4 3:2 1:0 Name TOS3F TOS3E TOS3D TOS3C Default PE3,RW PE3,RW PE3,RW PE3,RW Description If bit 53H.7 =1 :TOS[7:2]=3FH If bit 53H.7 =1 :TOS[7:2]=3EH If bit 53H.7 =1 :TOS[7:2]=3DH If bit 53H.7 =1 :TOS[7:2]=3CH 6.58 VLAN Priority Map Registers (D0H~D1H) D0H: Bit 7:6 5:4 3:2 1:0 D1H: Bit 7:6 5:4 3:2 1:0 Name TAG7 TAG6 TAG5 TAG4 Default PE3,RW PE3,RW PE2,RW PE2,RW Description VLAN priority tag value = 07H VLAN priority tag value = 06H VLAN priority tag value = 05H VLAN priority tag value = 04H Name TAG3 TAG2 TAG1 TAG0 Default PE1,RW PE1,RW PE0,RW PE0,RW Description VLAN priority tag value = 03H VLAN priority tag value = 02H VLAN priority tag value = 01H VLAN priority tag value = 00H 6.59 Memory Data Pre-Fetch Read Command without Address Increment Register (F0H) Bit Name Default Description 7:0 MRCMDX X,RO Read data from RX SRAM. After the read of this command, the read pointer of internal SRAM is unchanged. And the DM9013 starts to pre-fetch the SRAM data to internal data buffers. 6.60 Memory Data Read Command with Address Increment Register (F2H) When register FFH bit 7 is "0", register F5H value will be returned to 0000H, if 16K-byte boundary is reached. When register FFH bit 7 is "1", register F5H value will be returned to 0000H, if processor port receive memory byte boundary address RX memory size, defined in register 3FH with default 1F00H, is reached. Bit 7:0 Name MRCMD Default X,RO Description Read data from RX SRAM. After the read of this command, the read pointer is increased by 1,2, or 4, depends on the operator mode (8-bit,16-bit and 32-bit respectively) 6.61 Memory Data Read address Register (F4H) When register FFH bit 7 is "0", register F5H and F4H can be used as memory byte address to read internal 64K-byte memory. When register FFH bit 7 is "1", register F5H and F4H can be used as processor port receive memory byte address with memory space range from 0 to (RX memory size - 1), defined in register 3FH with default 1EFFH. Bit 7:0 36 Name MDRAL Default PHS0,RW Description Memory Data Read_ address Low Byte Preliminary datasheet DM9013-15-DS-P03 April 9, 2009 DM9013 3-port switch with Processor Interface 6.62 Memory Data Read address Register (F5H) Bit Name Default Description RESERVED 7-6 P0,RO Reserved 5:4 MDRAH65 PHS0,RW Port number 3:0 MDRAH40 PHS0,RW Memory Data Read_ address [11:8] 6.63 Memory Data Write Command without Address Increment Register (F6H) Bit Name Default Description 7:0 MWCMDX X,WO Write data to TX SRAM. After the write of this command, the write pointer is unchanged 6.64 Memory Data Write Command with Address Increment Register (F8H) Bit Name Default Description 7:0 MWCMD X,WO Write Data to TX SRAM After the write of this command, the write pointer is increased by 1, 2, or 4, depends on the operator mode. (8-bit, 16-bit,32-bit respectively) 6.65 Memory Data Write address Register (FAH) Bit Name Default Description 7:0 MDRAL PHS0,RW Memory Data Write_ address Low Byte 6.66 Memory Data Write address Register (FBH) Bit Name Default Description RESERVED 7,6 P0,RO Reserved 5:4 MDRAH65 PHS0,RW Port number 3:0 MDRAH40 PHS0,RW Memory Data Write_ address [11:8] 6.67 TX Packet Length Register (FCH~FDH) Bit Name Default 7:0 TXPLH PHS0,RW TX Packet Length High byte 7:0 TXPLL PHS0,RW TX Packet Length Low byte 6.68 Interrupt Status Register (FEH) Bit Name Default 7:6 IOMODE T0, RO Description Description Bit 7 Bit 6 0 0 16-bit mode 0 1 32-bit mode 1 0 8-bit mode 1 1 Reserved Link Status Change of port 0 or 1 BLK Table Counter error Receive Overflow Counter Overflow Receive Overflow Packet Transmitted Packet Received 5 4 3 2 1 0 LNKCHG CNT_ERR ROO ROS PT PR PHS0,RW/C1 PHS0,RW/C1 PHS0,RW/C1 PHS0,RW/C1 PHS0,RW/C1 PHS0,RW/C1 Preliminary datasheet DM9013-15-DS-P03 April 9, 2009 37 DM9013 3-port switch with Processor Interface 6.69 Interrupt Mask Register (FFH) Bit Name Default 7 TXRX_EN PHS0,RW 6 RESERVED 0,RO 5 LNKCHGI PHS0,RW 4 CNT_ERR PHS0,RW/C1 3 ROOI PHS0,RW 2 ROI PHS0,RW 1 PTI PHS0,RW 0 PRI PHS0,RW Description Enable the SRAM read/write pointer used as transmit /receive address. Reserved Enable Link Status Change of port 0 or 1Interrupt Enable BLK Table Counter error interrupt Enable Receive Overflow Counter Overflow Interrupt Enable Receive Overflow Interrupt Enable Packet Transmitted Interrupt Enable Packet Received Interrupt 38 Preliminary datasheet DM9013-15-DS-P03 April 9, 2009 DM9013 3-port switch with Processor Interface 7. EEPROM Format name MAC address Auto Load Control Word 0~2 3 Description 6 Byte Ethernet Address Bit 1:0=01: Update vendor ID and product ID Bit 3:2=01: Accept setting of WORD6 [4:0] Bit 5:4= reserved Bit 7:6=01: Accept setting of WORD7 [3:0] Bit 9:8=Reserved Bit 11:10= Reserved, set to 00 in application Bit 13:12= Reserved Bit 15:14=01: Accept setting of WORD7 [15:14] 2 byte vendor ID (Default: 0A46H) 2 byte product ID (Default: 9013H) When word 3 bit [3:2] =01, these bits can control the CS#, IOR#, IOW# and IRQ pins polarity. Bit0: CS# pin is active high when set (default active low) Bit1: IOR# pin is active high when set (default: active low) Bit2: IOW# pin is active high when set (default: active low) Bit3: IRQ pin is active low when set (default: active high) Bit4: IRQ pin is open-collected (default: force output) Bit 15:5: Reserved Bit0: The WOL pin is active low when set (default: active high) Bit1: The WOL pin is in pulse mode when set (default: level mode) Bit2: Reserved Bit3: Reserved Bit 13:12 reserved, set to 00 in application Bit14: Port 1 AUTO-MDIX control 1: ON, 0: OFF(default ON) Bit15: Port 0 AUTO-MDIX control 1: ON, 0: OFF(default ON) Reserved Bit 1:0=01: Accept setting of WORD 17,18 Bit 3:2=01: Accept setting of WORD 19~26 Bit 5:4=01: Accept setting of WORD 27~30 Bit 7:6=01: Accept setting of WORD 31 Bit 9:8=01: Accept setting of WORD 32~39 Bit 11:10=01: Accept setting of WORD 40~47 Bit 15:12 = Reserved, set to 0000 in application When word 16 bit 1:0 is "01", after power on reset: This word bit 7~0 will be loaded to Reg. 52H bit 7~0 This word bit 15~8 will be loaded to Reg. 53H bit 7~0 This word must be cleared to 0000, if word 16 bit [1:0]=01 When word 16 bit 3:2 is "01", after power on reset: This word bit 7~0 will be loaded to port 0 Reg. 61H bit 7~0 This word bit 15~8 will be loaded to port 0 Reg. 66H bit 7~0 When word 16 bit 3:2 is "01", after power on reset: This word bit 7~0 will be loaded to port 0 Reg. 67H bit 7~0 This word bit 15~8 will be loaded to port 0 Reg. 6DH bit 7~0 When word 16 bit 3:2 is "01", after power on reset: This word bit 7~0 will be loaded to port 1 Reg. 61H bit 7~0 39 Vendor ID Product ID pin control 4 5 6 PHY control 7 RESERVED Control 8~15 16 Switch Control 1 17 RESERVED Port 0 Control 1 18 19 Port 0 Control 2 20 Port 1 Control 1 21 Preliminary datasheet DM9013-15-DS-P03 April 9, 2009 DM9013 3-port switch with Processor Interface Port 1 Control 2 22 This word bit 15~8 will be loaded to port 1 Reg. 66H bit 7~0 When word 16 bit 3:2 is "01", after power on reset: This word bit 7~0 will be loaded to port 1 Reg. 67H bit 7~0 This word bit 15~8 will be loaded to port 1 Reg. 6DH bit 7~0 When word 16 bit 3:2 is "01", after power on reset: This word bit 7~0 will be loaded to port 2 Reg. 61H bit 7~0 This word bit 15~8 will be loaded to port 2 Reg. 66H bit 7~0 When word 16 bit 3:2 is "01", after power on reset: This word bit 7~0 will be loaded to port 2 Reg. 67H bit 7~0 This word bit 15~8 will be loaded to port 2 Reg. 6DH bit 7~0 When word 16 bit 3:2 is "01", after power on reset: This word bit 7~0 will be loaded to port 3 Reg. 61H bit 7~0 This word bit 15~8 will be loaded to port 3 Reg. 66H bit 7~0 When word 16 bit 3:2 is "01", after power on reset: This word bit 7~0 will be loaded to port 3 Reg. 67H bit 7~0 This word bit 15~8 will be loaded to port 3 Reg. 6DH bit 7~0 When word 16 bit 5:4 is "01", after power on reset: This word bit 7~0 will be loaded to port 0 Reg. 6EH bit 7~0 This word bit 15~8 will be loaded to port 0 Reg. 6FH bit 7~0 When word 16 bit 5:4 is "01", after power on reset: This word bit 7~0 will be loaded to port 1 Reg. 6EH bit 7~0 This word bit 15~8 will be loaded to port 1 Reg. 6FH bit 7~0 When word 16 bit 5:4 is "01", after power on reset: This word bit 7~0 will be loaded to port 2 Reg. 6EH bit 7~0 This word bit 15~8 will be loaded to port 2 Reg. 6FH bit 7~0 When word 16 bit 5:4 is "01", after power on reset: This word bit 7~0 will be loaded to port 3 Reg. 6EH bit 7~0 This word bit 15~8 will be loaded to port 3 Reg. 6FH bit 7~0 When word 16 bit 7:6 is "01", after power on reset: This word bit 7~0 will be loaded to Reg. D0H bit 7~0 This word bit 15~8 will be loaded to Reg. D1H bit 7~0 When word 16 bit 9:8 is "01", after power on reset: This word bit 7~0 will be loaded to Reg. B0H bit 7~0 This word bit 15~8 will be loaded to Reg. B1H bit 7~0 When word 16 bit 9:8 is "01", after power on reset: This word bit 7~0 will be loaded to Reg. B2H bit 7~0 This word bit 15~8 will be loaded to Reg. B3H bit 7~0 When word 16 bit 9:8 is "01", after power on reset: This word bit 7~0 will be loaded to Reg. B4H bit 7~0 This word bit 15~8 will be loaded to Reg. B5H bit 7~0 When word 16 bit 9:8 is "01", after power on reset: This word bit 7~0 will be loaded to Reg. B6H bit 7~0 This word bit 15~8 will be loaded to Reg. B7H bit 7~0 When word 16 bit 9:8 is "01", after power on reset: This word bit 7~0 will be loaded to Reg. B8H bit 7~0 This word bit 15~8 will be loaded to Reg. B9H bit 7~0 When word 16 bit 9:8 is "01", after power on reset: This word bit 7~0 will be loaded to Reg. BAH bit 7~0 This word bit 15~8 will be loaded to Reg. BBH bit 7~0 When word 16 bit 9:8 is "01", after power on reset: Preliminary datasheet DM9013-15-DS-P03 April 9, 2009 Port 2 Control 1 23 Port 2 Control 2 24 uP Port Control 1 25 uP Port Control 2 26 Port 0 VLAN Tag 27 Port 1 VLAN Tag 28 Port 2 VLAN Tag 29 uP Port VLAN Tag 30 VLAN Priority Map 31 Port VLAN Group 0,1 Port VLAN Group 2,3 Port VLAN Group 4,5 Port VLAN Group 6,7 Port VLAN Group 8,9 Port VLAN Group 10,11 Port VLAN Group 40 32 33 34 35 36 37 38 DM9013 3-port switch with Processor Interface 12,13 Port VLAN Group 14,15 ToS Priority Map 0 39 This word bit 7~0 will be loaded to Reg. BCH bit 7~0 This word bit 15~8 will be loaded to Reg. BDH bit 7~0 When word 16 bit 9:8 is "01", after power on reset: This word bit 7~0 will be loaded to Reg. BEH bit 7~0 This word bit 15~8 will be loaded to Reg. BFH bit 7~0 When word 16 bit 11:10 is "01", after power on reset: This word bit 7~0 will be loaded to Reg. C0H bit 7~0 This word bit 15~8 will be loaded to Reg. C1H bit 7~0 When word 16 bit 11:10 is "01", after power on reset: This word bit 7~0 will be loaded to Reg. C2H bit 7~0 This word bit 15~8 will be loaded to Reg. C3H bit 7~0 When word 16 bit 11:10 is "01", after power on reset: This word bit 7~0 will be loaded to Reg. C4H bit 7~0 This word bit 15~8 will be loaded to Reg. C5H bit 7~0 When word 16 bit 11:10 is "01", after power on reset: This word bit 7~0 will be loaded to Reg. C6H bit 7~0 This word bit 15~8 will be loaded to Reg. C7H bit 7~0 When word 16 bit 11:10 is "01", after power on reset: This word bit 7~0 will be loaded to Reg. C8H bit 7~0 This word bit 15~8 will be loaded to Reg. C9H bit 7~0 When word 16 bit 11:10 is "01", after power on reset: This word bit 7~0 will be loaded to Reg. CAH bit 7~0 This word bit 15~8 will be loaded to Reg. CBH bit 7~0 When word 16 bit 11:10 is "01", after power on reset: This word bit 7~0 will be loaded to Reg. CCH bit 7~0 This word bit 15~8 will be loaded to Reg. CDH bit 7~0 When word 16 bit 11:10 is "01", after power on reset: This word bit 7~0 will be loaded to Reg. CEH bit 7~0 This word bit 15~8 will be loaded to Reg. CFH bit 7~0 40 ToS Priority Map 1 41 ToS Priority Map 2 42 ToS Priority Map 3 43 ToS Priority Map 4 44 ToS Priority Map 5 45 ToS Priority Map 6 46 ToS Priority Map 7 47 Preliminary datasheet DM9013-15-DS-P03 April 9, 2009 41 DM9013 3-port switch with Processor Interface 8. PHY Registers MII Register Description ADD Name 15 00H CONTR Reset OL 0 01H STATUS T4 Cap. 0 02H PHYID1 0 03H PHYID2 1 04H Auto-Neg. Next Advertise Page 05H Link Part. LP Ability Next Page 06H Auto-Neg. Expansio n 10H Specifie BP d 4B5B Config. 11H Specifie 100 FDX d Conf/Stat 12H 10T Rsvd Conf/Stat 13H PWDOR 14 Loop back 0 TX FDX Cap. 1 0 0 FLP Rcv Ack LP Ack 13 12 11 Speed Auto-N Power select Enable Down 1 1 0 TX HDX 10 FDX 10 HDX Cap. Cap. Cap. 1 1 1 0 0 0 1 1 1 Remote Fault LP RF Reserved Reserved 10 Isolate 0 9 8 Restart Full Auto-N Duplex 0 1 Reserved 7 Coll. Test 0 6 5 4 3 Reserved 2 1 0 0 0 FC Adv LP FC Reserved Pream. Auto-N Supr. Compl. 0000 1 0 0 1 1 0 0 Model No. 01011 T4 TX FDX TX HDX 10 FDX 10 HDX Adv Adv Adv Adv Adv LP LP LP LP LP T4 TX FDX TX HDX 10 FDX 10 HDX Remote Fault 0 0 000_0000 Auto-N Link Jabber Cap. Status Detect 1 0 0 0 0 0 Version No. 0000 Advertised Protocol Selector Field Link Partner Protocol Selector Field Extd Cap. 1 1 Pardet Fault LP Next Pg Able Next Pg Able Pream. Supr. New Pg LP AutoN Rcv Cap. Sleep mode Remote LoopOut BP SCR 100 HDX LP Enable BP BP_ADP Reserve ALIGN OK dr 10 FDX HBE Enable TX Reserve Reserve Force Reserve Reserve RPDCTR Reset d d 100LNK d d -EN St. Mch PHY ADDR [4:0] Reserved PD10DR PD100l V PDchip PDcrm PDaeq PDdrv 10 HDX Reserve Reverse Reverse d d d SQUE Enable Reserved JAB Enable Reserve d Auto-N. Monitor Bit [3:0] Polarity Reverse PDecli PDeclo PD10 14H Specifie TSTSE TSTSE FORCE FORCE PREA TX10M NWAY Reserv MDIX_ AutoNe Mdix_fix Mdix_d MonSel MonSel Reserv PD_val d config 1 2 _TXSD _FEF MBLEX _PWR _PWR ed CNTL g_dlpbk Value own 1 0 ed ue 16H RCVER 17H DIS_conn ect Reversed Receiver Error Counter Disconnect_counter 1DH PSCR Reversed PREA AMPLIT TX_P MBLE UDE WR X Reversed Key to Default In the register description that follows, the default column takes the form: 42 Preliminary datasheet DM9013-15-DS-P03 April 9, 2009 DM9013 3-port switch with Processor Interface 8.1 Basic Mode Control Register (BMCR) - 00H Bit 15 Bit Name Reset Default Description 0, RW/SC Reset 0=Normal operation 1=Software reset This bit sets the status and controls the PHY registers to their default states. This bit, which is self-clearing, will keep returning a value of one until the reset process is completed 0, RW Loopback Loop-back control register 0 = Normal operation 1 = Loop-back enabled When in 100Mbps operation mode, setting this bit may cause the descrambler to lose synchronization and produce a 720ms "dead time" before any valid data appears at the MII receive outputs 1, RW Speed Select 0 = 10Mbps 1 = 100Mbps Link speed may be selected either by this bit or by auto-negotiation. When auto-negotiation is enabled and bit 12 is set, this bit will return auto-negotiation selected medium type 1, RW Auto-negotiation Enable 0= Auto-negotiation is disabled 1 = Auto-negotiation is enabled, bit 8 and 13 will be in auto-negotiation status 0, RW Power Down While in the power-down state, the PHY should respond to management transactions. During the transition to power-down state and while in the power-down state, the PHY should not generate spurious signals on the MII 0=Normal operation 1=Power down 0,RW Isolate Force to 0 in application. 0,RW/SC Restart Auto-negotiation 0 = Normal operation 1 = Restart auto-negotiation. Re-initiates the auto-negotiation process. When auto-negotiation is disabled (bit 12 of this register cleared), this bit has no function and it should be cleared. This bit is self-clearing and it will keep returning to a value of 1 until auto-negotiation is initiated by the DM9013. The operation of the auto-negotiation process will not be affected by the management entity that clears this bit 1,RW Duplex Mode 0 = Normal operation 1 = Full duplex operation. Duplex selection is allowed when Auto-negotiation is disabled (bit 12 of this register is cleared). With auto-negotiation enabled, this bit reflects the duplex capability 43 14 Loopback 13 Speed selection 12 Auto-negotiation enable 11 Power down 10 9 Isolate Restart Auto-negotiation 8 Duplex mode Preliminary datasheet DM9013-15-DS-P03 April 9, 2009 DM9013 3-port switch with Processor Interface selected by auto-negotiation 7 Collision test 0,RW 6-0 Reserved 0,RO Collision Test 0 = Normal operation 1 = Collision test enabled. When set, this bit will cause the COL signal to be asserted in response to the assertion of TX_EN in internal MII interface. Reserved Read as 0, ignore on write 8.2 Basic Mode Status Register (BMSR) - 01H Bit 15 Bit Name 100BASE-T4 Default 0,RO/P Description 100BASE-T4 Capable 0 = not able to perform in 100BASE-T4 mode 1 = able to perform in 100BASE-T4 mode 100BASE-TX Full Duplex Capable 0 = not able to perform 100BASE-TX in full duplex mode 1 = able to perform 100BASE-TX in full duplex mode 100BASE-TX Half Duplex Capable 0 = not able to perform 100BASE-TX in half duplex mode 1 = able to perform 100BASE-TX in half duplex mode 10BASE-T Full Duplex Capable 0 = not able to perform 10BASE-TX in full duplex mode 1 = able to perform 10BASE-T in full duplex mode 10BASE-T Half Duplex Capable 0 = not able to perform 10BASE-T in half duplex mode 1 = able to perform 10BASE-T in half duplex mode Reserved Read as 0, ignore on write MII Frame Preamble Suppression 0 = not accept management frames with preamble suppressed 1 = accept management frames with preamble suppressed Auto-negotiation Complete 0 = Auto-negotiation process not completed 1 = Auto-negotiation process completed Remote Fault 0 = No remote fault condition detected 1 = Remote fault condition detected (cleared on read or by a chip reset). Fault criteria and detection method is DM9013 implementation specific. This bit will set after the RF bit in the ANLPAR (bit 13, register address 05) is set Auto Configuration Ability 0 = not able to perform auto-negotiation 1 = able to perform auto-negotiation Link Status 0 = Link is not established Preliminary datasheet DM9013-15-DS-P03 April 9, 2009 14 100BASE-TX full-duplex 100BASE-TX half-duplex 10BASE-T full-duplex 10BASE-T half-duplex Reserved MF preamble suppression Auto-negotiation Complete Remote fault 1,RO/P 13 1,RO/P 12 1,RO/P 11 1,RO/P 10-7 6 0,RO 1,RO 5 0,RO 4 0, RO 3 Auto-negotiation ability Link status 1,RO/P 2 44 0,RO DM9013 3-port switch with Processor Interface 1 = Valid link is established (for either 10Mbps or 100Mbps operation) The link status bit is implemented with a latching function, so that the occurrence of a link failure condition causes the link status bit to be cleared and remain cleared until it is read via the management interface Jabber Detect 0 = No jabber 1 = Jabber condition detected This bit is implemented with a latching function. Jabber conditions will set this bit unless it is cleared by a read to this register through a management interface or a DM9013 reset. This bit works only in 10Mbps mode Extended Capability 0 = Basic register capable only 1 = Extended register capable 1 Jabber detect 0, RO 0 Extended capability 1,RO/P 8.3 PHY ID Identifier Register #1 (PHYID1) - 02H The PHY Identifier Registers #1 and #2 work together in a single identifier of the DM9013. The Identifier consists of a concatenation of the Organizationally Unique Identifier (OUI), a vendor's model number, and a model revision number. DAVICOM Semiconductor's IEEE assigned OUI is 00606E. Bit 15-0 Bit Name OUI_MSB Default <0181h> Description OUI Most Significant Bits This register stores bit 3 to 18 of the OUI (00606E) to bit 15 to 0 of this register respectively. The most significant two bits of the OUI are ignored (the IEEE standard refers to these as bit 1 and 2) 8.4 PHY ID Identifier Register #2 (PHYID2) - 03H Bit 15-10 Bit Name OUI_LSB Default <101110>, RO/P <001011>, RO/P <0000>, RO/P Description OUI Least Significant Bits Bit 19 to 24 of the OUI (00606E) are mapped to bit 15 to 10 of this register respectively Vendor Model Number Five bits of vendor model number mapped to bit 9 to 4 (most significant bit to bit 9) Model Revision Number Five bits of vendor model revision number mapped to bit 3 to 0 (most significant bit to bit 4) 9-4 VNDR_MDL 3-0 MDL_REV Preliminary datasheet DM9013-15-DS-P03 April 9, 2009 45 DM9013 3-port switch with Processor Interface 8.5 Auto-negotiation Advertisement Register (ANAR) - 04H This register contains the advertised abilities of this DM9013 device as they will be transmitted to its link partner during Auto-negotiation. Bit 15 Bit Name NP Description Next page Indication 0 = No next page available 1 = Next page available The DM9013 has no next page, so this bit is permanently set to 0 0,RO Acknowledge 0 = Not acknowledged 1 = Link partner ability data reception acknowledged The DM9013's auto-negotiation state machine will automatically control this bit in the outgoing FLP bursts and set it at the appropriate time during the auto-negotiation process. Software should not attempt to write to this bit. 0, RW Remote Fault 0 = No fault detected 1 = Local device senses a fault condition X, RW Reserved Write as 0, ignore on read 1, RW Flow Control Support 0 = Controller chip doesn't support flow control ability 1 = Controller chip supports flow control ability 0, RO/P 100BASE-T4 Support 0 = 100BASE-T4 is not supported 1 = 100BASE-T4 is supported by the local device The DM9013 does not support 100BASE-T4 so this bit is permanently set to 0 1, RW 100BASE-TX Full Duplex Support 0 = 100BASE-TX full duplex is not supported 1 = 100BASE-TX full duplex is supported by the local device 1, RW 100BASE-TX Support 0 = 100BASE-TX half duplex is not supported 1 = 100BASE-TX half duplex is supported by the local device 1, RW 10BASE-T Full Duplex Support 0 = 10BASE-T full duplex is not supported 1 = 10BASE-T full duplex is supported by the local device 1, RW 10BASE-T Support 0 = 10BASE-T half duplex is not supported 1 = 10BASE-T half duplex is supported by the local device <00001>, RW Protocol Selection Bits These bits contain the binary encoded protocol selector supported by this node <00001> indicates that this device supports IEEE 802.3 CSMA/CD Default 0,RO/P 14 ACK 13 RF 12-11 10 Reserved FCS 9 T4 8 TX_FDX 7 TX_HDX 6 10_FDX 5 10_HDX 4-0 Selector 46 Preliminary datasheet DM9013-15-DS-P03 April 9, 2009 DM9013 3-port switch with Processor Interface 8.6 Auto-negotiation Link Partner Ability Register (ANLPAR) - 05H This register contains the advertised abilities of the link partner when received during Auto-negotiation. Bit 15 Bit Name NP Description Next Page Indication 0 = Link partner, no next page available 1 = Link partner, next page available 0, RO Acknowledge 0 = Not acknowledged 1 = Link partner ability data reception acknowledged The DM9013's auto-negotiation state machine will automatically control this bit from the incoming FLP bursts. Software should not attempt to write to this bit 0, RO Remote Fault 0 = No remote fault indicated by link partner 1 = Remote fault indicated by link partner 0, RO Reserved Read as 0, ignore on write 0, RO Flow Control Support 0 = Controller chip doesn't support flow control ability by link partner 1 = Controller chip supports flow control ability by link partner 0, RO 100BASE-T4 Support 0 = 100BASE-T4 is not supported by the link partner 1 = 100BASE-T4 is supported by the link partner 0, RO 100BASE-TX Full Duplex Support 0 = 100BASE-TX full duplex is not supported by the link partner 1 = 100BASE-TX full duplex is supported by the link partner 0, RO 100BASE-TX Support 0 = 100BASE-TX half duplex is not supported by the link partner 1 = 100BASE-TX half duplex is supported by the link partner 0, RO 10BASE-T Full Duplex Support 0 = 10BASE-T full duplex is not supported by the link partner 1 = 10BASE-T full duplex is supported by the link partner 0, RO 10BASE-T Support 0 = 10BASE-T half duplex is not supported by the link partner 1 = 10BASE-T half duplex is supported by the link partner <00000>, RO Protocol Selection Bits Link partner's binary encoded protocol selector Default 0, RO 14 ACK 13 RF 12-11 10 Reserved FCS 9 T4 8 TX_FDX 7 TX_HDX 6 10_FDX 5 10_HDX 4-0 Selector Preliminary datasheet DM9013-15-DS-P03 April 9, 2009 47 DM9013 3-port switch with Processor Interface 8.7 Auto-negotiation Expansion Register (ANER) - 06H Bit 15-5 4 Bit Name Reserved PDF Default 0, RO 0, RO/LH Description Reserved Read as 0, ignore on write Local Device Parallel Detection Fault PDF = 1: A fault detected via parallel detection function. PDF = 0: No fault detected via parallel detection function Link Partner Next Page Able LP_NP_ABLE = 1: Link partner, next page available LP_NP_ABLE = 0: Link partner, no next page Local Device Next Page Able NP_ABLE = 1: DM9013, next page available NP_ABLE = 0: DM9013, no next page DM9013 does not support this function, so this bit is always 0 New Page Received A new link code word page received. This bit will be automatically cleared when the register (register 6) is read by management Link Partner Auto-negotiation Able A "1" in this bit indicates that the link partner supports Auto-negotiation 3 LP_NP_ABLE 0, RO 2 NP_ABLE 0,RO/P 1 PAGE_RX 0, RO 0 LP_AN_ABLE 0, RO 8.8 DAVICOM Specified Configuration Register (DSCR) - 10H Bit Bit Name Default Description 15 BP_4B5B 0,RW Bypass 4B5B Encoding and 5B4B Decoding 0 = Normal 4B5B and 5B4B operation 1 = 4B5B encoder and 5B4B decoder function bypassed 14 BP_SCR 0, RW Bypass Scrambler/Descrambler Function 0 = Normal scrambler and descrambler operation 1 = Scrambler and descrambler function bypassed 13 BP_ALIGN 0, RW Bypass Symbol Alignment Function 0 = Normal operation 1 = Receive functions (descrambler, symbol alignment and symbol decoding functions) bypassed. Transmit functions (symbol encoder and scrambler) bypassed 12 BP_ADPOK 0, RW BYPASS ADPOK Force signal detector (SD) active. This register is for debug only, not release to customer 0=Normal operation 1=Forced SD is OK, 11 Reserved RW Reserved Force to 0 in application 10 TX 1, RW 100BASE-TX Mode Control 0 = 100BASE-FX operation 1 = 100BASE-TX operation 9 Reserved 0, RO Reserved 8 Reserved 0, RW Reserved 7 F_LINK_100 0, RW Force Good Link in 100Mbps 0 = Normal 100Mbps operation 48 Preliminary datasheet DM9013-15-DS-P03 April 9, 2009 DM9013 3-port switch with Processor Interface 6 5 4 Reserved COL_LED RPDCTR-EN 0, RW 0, RW 1, RW 1 = Force 100Mbps good link status This bit is useful for diagnostic purposes Reserved Force to 0 in application. COL LED Control (valid in PHY test mode) Reduced Power Down Control Enable This bit is used to enable automatic reduced power down 0 = Disable automatic reduced power down 1 = Enable automatic reduced power down Reset State Machine When writes 1 to this bit, all state machines of PHY will be reset. This bit is self-clear after reset is completed MF Preamble Suppression Control MII frame preamble suppression control bit 0 = MF preamble suppression bit off 1 = MF preamble suppression bit on Sleep Mode Writing a 1 to this bit will cause PHY entering the Sleep mode and power down all circuit except oscillator and clock generator circuit. When waking up from Sleep mode (write this bit to 0), the configuration will go back to the state before sleep; but the state machine will be reset Remote Loop out Control When this bit is set to 1, the received data will loop out to the transmit channel. This is useful for bit error rate testing 3 SMRST 0, RW 2 MFPSC 1, RW 1 SLEEP 0, RW 0 RLOUT 0, RW Preliminary datasheet DM9013-15-DS-P03 April 9, 2009 49 DM9013 3-port switch with Processor Interface 8.9 DAVICOM Specified Configuration and Status Register (DSCSR) - 11H Bit 15 Bit Name 100FDX Default 1, RO Description 100M Full Duplex Operation Mode After auto-negotiation is completed, results will be written to this bit. If this bit is 1, it means the operation 1 mode is a 100M full duplex mode. The software can read bit [15:12] to see which mode is selected after auto-negotiation. This bit is invalid when it is not in the auto-negotiation mode 100M Half Duplex Operation Mode After auto-negotiation is completed, results will be written to this bit. If this bit is 1, it means the operation 1 mode is a 100M half duplex mode. The software can read bit [15:12] to see which mode is selected after auto-negotiation. This bit is invalid when it is not in the auto-negotiation mode 10M Full Duplex Operation Mode After auto-negotiation is completed, results will be written to this bit. If this bit is 1, it means the operation 1 mode is a 10M Full Duplex mode. The software can read bit [15:12] to see which mode is selected after auto-negotiation. This bit is invalid when it is not in the auto-negotiation mode 10M Half Duplex Operation Mode After auto-negotiation is completed, results will be written to this bit. If this bit is 1, it means the operation 1 mode is a 10M half duplex mode. The software can read bit [15:12] to see which mode is selected after auto-negotiation. This bit is invalid when it is not in the auto-negotiation mode Reserved Read as 0, ignore on write Reserved PHY Address Bit 4:0 The first PHY address bit transmitted or received is the MSB of the address (bit 4). A station management entity connected to multiple PHY entities must know the appropriate address of each PHY Auto-negotiation Monitor Bits These bits are for debug only. The auto-negotiation status will be written to these bits. B3 b2 b1 B0 0 0 0 0 In IDLE state 0 0 0 1 Ability match 0 0 1 0 Acknowledge match 0 0 1 1 Acknowledge match fail 0 1 0 0 Consistency match 0 1 0 1 Consistency match fail 0 1 1 0 Parallel detects signal link ready 0 1 1 1 Parallel detects signal link ready fail 1 0 0 0 Auto-negotiation completed successfully 14 100HDX 1, RO 13 10FDX 1, RO 12 10HDX 1, RO 11 10-9 8-4 Reserved Reserved PHYADR[4 :0] 0, RO 0,RW 1, RW 3-0 ANMB[3:0] 0, RO 50 Preliminary datasheet DM9013-15-DS-P03 April 9, 2009 DM9013 3-port switch with Processor Interface 8.10 10BASE-T Configuration/Status (10BTCSR) - 12H Bit 15 14 Bit Name Reserved LP_EN Default 0, RO 1, RW Description Reserved Read as 0, ignore on write Link Pulse Enable 0 = Link pulses disabled, good link condition forced 1 = Transmission of link pulses enabled This bit is valid only in 10Mbps operation Heartbeat Enable 0 = Heartbeat function disabled 1 = Heartbeat function enabled When the DM9013 is configured for full duplex operation, this bit will be ignored (the collision/heartbeat function is invalid in full duplex mode) Squelch Enable 0 = Low squelch 1 = Normal squelch Jabber Enable Enables or disables the Jabber function when the DM9013 is in 10BASE-T full duplex or 10BASE-T transceiver Loopback mode 0 = Jabber function disabled 1 = Jabber function enabled 10M Serial Mode (valid in PHY test mode) Force to 0, in application. Reserved Read as 0, ignore on write Polarity Reversed When this bit is set to 1, it indicates that the 10Mbps cable polarity is reversed. This bit is automatically set and cleared by 10BASE-T module 13 HBE 1,RW 12 SQUELCH 1, RW 11 JABEN 1, RW 10 9-1 0 SERIAL Reserved POLR 0, RW 0, RO 0, RO 8.11 Power Down Control Register (PWDOR) - 13H Description Reserved Read as 0, ignore on write 8 PD10DRV 0, RW Vendor power down control test 7 PD100DL 0, RW Vendor power down control test 6 PDchip 0, RW Vendor power down control test 5 PDcrm 0, RW Vendor power down control test 4 PDaeq 0, RW Vendor power down control test 3 PDdrv 0, RW Vendor power down control test 2 PDedi 0, RW Vendor power down control test 1 PDedo 0, RW Vendor power down control test 0 PD10 0, RW Vendor power down control test * When selected, the power down value is control by Register 20.0 Bit 15-9 Bit Name Reserved Default 0, RO Preliminary datasheet DM9013-15-DS-P03 April 9, 2009 51 DM9013 3-port switch with Processor Interface 8.12 (Specified config) Register - 14H Bit 15 14 13 Description Vendor test select control Vendor test select control Force Signal Detect 0: normal SD signal. 1: force SD signal OK in 100M FORCE_FEF 0,RW Vendor test select control PREAMBLEX 0,RW Preamble Saving Control 0: when bit 10 is set, the 10M TX preamble count is reduced. When bit 11 of register 29 is set, 12-bit preamble bit is reduced; otherwise 22-bit preamble bits is reduced. 1: 10M TX preamble bit count is normal. TX10M_PWR 1,RW 10M TX Power Saving Control 1: enable 10M TX power saving 0: disable 10M TX power saving NWAY_PWR 0,RW N-Way Power Saving Control 1: disable N-Way power saving 0: enable N-Way power saving Reserved 0, RO Reserved Read as 0, ignore on write MDIX_CNTL MDI/MDIX,RO The polarity of MDI/MDIX value 0: MDI mode 1: MDIX mode AutoNeg_dpbk 0,RW Auto-negotiation Loopback 0: normal. 1: test internal digital auto-negotiation Loopback Mdix_fix Value 0, RW MDIX_CNTL force value: When Mdix_down = 1, MDIX_CNTL value depend on the register value. Mdix_down 0,RW MDIX Down Manual force MDI/MDIX. 0: Enable HP Auto-MDIX 1: Disable HP Auto-MDIX , MDIX_CNTL value depend on 20.5 MonSel1 0,RW Vendor monitor select MonSel0 0,RW Vendor monitor select Reserved 0,RW Reserved Force to 0, in application. PD_value 0,RW Power down control value Decision the value of each field Register 19. 0: normal 1: power down Bit Name TSTSE1 TSTSE2 FORCE_TXSD Default 0,RW 0,RW 0,RW 12 11 10 9 8 7 6 5 4 3 2 1 0 52 Preliminary datasheet DM9013-15-DS-P03 April 9, 2009 DM9013 3-port switch with Processor Interface 8.13 DAVICOM Specified Receive Error Counter Register (RECR) - 16H Bit 15-0 Bit Name Rcv_ Err_ Cnt Default 0, RO Description Receive Error Counter Receive error counter that increments upon detection of RXER. Clean by read this register. 8.14 DAVICOM Specified Disconnect Counter Register (DISCR) - 17H Bit 15-8 7-0 Bit Name Reserved Disconnect Counter Default 0, RO 0, RO Description Reserved Disconnect Counter that increment upon detection of disconnection. Clean by read this register. 8.15 Power Saving Control Register (PSCR) - 1DH Bit 15-12 11 Bit Name RESERVED PREAMBLEX Default 0,RO 0,RW Description RESERVED Preamble Saving Control when both bit 10and 11 of register 20 are set, the 10M TX preamble count is reduced. 1: 12-bit preamble bit is reduced. 0: 22-bit preamble bits is reduced. 10M TX Amplitude Control Disabled 1: when cable is unconnected with link partner, the TX amplitude is reduced for power saving. 0: disable TX amplitude reduce function TX Power Saving Control Disabled 1: when cable is unconnected with link partner, the driving current of transmit is reduced for power saving. 0: disable TX driving power saving function RESERVED 10 AMPLITUDE 0,RW 9 TX_PWR 0.RW 8-0 RESERVED 0,RO Preliminary datasheet DM9013-15-DS-P03 April 9, 2009 53 DM9013 3-port switch with Processor Interface 9. Functional Description 9.1 Processor bus and memory management function: 9.1.1 Processor Interface In the general processor mode, the chip selection is just coming from pin 2 (CS#). There are only two addressing ports through the access of the host interface. One port is the INDEX port and the other is the DATA port. The INDEX port is decoded by the CMD pin=0 and the DATA by the CMD pin=1. The contents of the INDEX port are the register address of the DATA port. Before the access of any register, the address of the register must be saved in the INDEX port before. 9.1.2 Direct Memory Access Control The DM9013 provides DMA capability to simplify the access of the internal memory. After the setting of the starting address of the internal memory and then issuing a dummy read/write command to load the current data to internal data buffer, the desired location of the internal memory can be accessed by the read/write command registers. The memory's address will be increased with the size equal to the current operation mode (i.e. the byte, word or double-word mode) and the data of the next location will be loaded to internal data buffer automatically. It is noted that the data of the first access (the dummy read/write command) in a sequential burst should be ignored because that the data was the contents of the last read/write command. There are two configured types of internal memory which are controlled by bit 7 of IMR. When the bit 7 of IMR is set, the internal memory is used for transmit and receive buffers. The transmit buffer occupies 7.5K bytes in 3-port mode and 8K bytes in 2-port mode. And the receive buffer occupies 7.5K bytes in 3-port mode and 7.75K bytes in 2-port mode. Both the transmit and receive buffer address need not to be programmed instead that they are managed by the DM9013 automatically. In transmit function, after power on reset or each time after the transmit command is issued (bit 0 of TCR is set), the next starting transmit buffer address is loaded. In receive function, the 7.5K-byte (or 7.75K-byte) receive buffer can be treated as a continued logic memory space. The memory address will wrap to address 0 if the end of address is reached. When the bit 7 of IMR is cleared, there is a 64Kbyte memory space in the DM9013 can be accessed. This configured type of internal memory is used for testing only. The memory write address (register FAh/FBh) and the memory read address (register F4h/F5h) represent the physical memory address of the DM9013 internal memory. It is noted that after the memory had been written by memory write command, the switch reset command (bit 6 of register 52h) should be set before normal switch function operation, since the controlled data in internal memory may be corrupted. 9.1.3 Packet Transmission There are two packets, sequentially named as index I and index II, can be stored in the TX SRAM at the same time. The index register 02h controls the insertion of CRC. The start address of transmission is 00h and the current packet is index I after software or hardware reset. Firstly write data to the TX SRAM using the DMA port and then write the byte count to byte count register at index register 0fch and 0fdh. Set the bit 1 of control register. The DM9013 starts to transmit the index I packet. Before the transmission of the index I packet ends, the data of the next (index II) packet can be moved to TX SRAM. After the index I packet ends the transmission, write the byte count data of the index II to BYTE_COUNT register and then set the bit 1 of control register to transmit the index II packet. The following packets, named index I, II, I, II... use the same way to be transmitted. 9.1.4 Packet Reception The RX SRAM is a ring data structure. Each packet has a 4-byte header followed with the data of the reception packet which CRC field is included. The format of the 4-byte header is 01h, status, BYTE_COUNT low, and BYTE_COUNT high. It is noted that the start address of each packet is in the proper address boundary which depends on the operation mode (byte, word, or double-word mode). 54 Preliminary datasheet DM9013-15-DS-P03 April 9, 2009 DM9013 3-port switch with Processor Interface 9.2 Switch function: 9.2.1 Address Learning The DM9013 has a self-learning mechanism for learning the MAC addresses of incoming packets in real time. DM9013 stores MAC addresses, port number and time stamp information in the Hash-based Address Table. It can learn up to 1K unicast address entry. The switch engine updates address table with new entry if incoming packet's Source Address (SA) does not exist and incoming packet is valid (non-error and legal length). Besides, DM9013 has an option to disable address learning for individual port. This feature can be set by bit 0 of register 65h 9.2.2 Address Aging The time stamp information of address table is used in the aging process. The switch engine updates time stamp whenever the corresponding SA receives. The switch engine would delete the entry if its time stamp is not updated for a period of time. The period can be programmed or disabled through bit 0 & 1 of register 52h. 9.2.3 Packet Forwarding The DM9013 forwards the incoming packet according to following decision: (1). If DA is Multicast/Broadcast, the packet is forwarded to all ports, except to the port on which the packet was received. (2). Switch engine would look up address table based on DA when incoming packets is UNICAST. If the DA was not found in address table, the packet is treated as a multicast packet and forward to other ports. If the DA was found and its destination port number is different to source port number, the packet is forward to destination port. (3). Switch engine also look up VLAN, Port Monitor setting and other forwarding constraints for the forwarding decision, more detail will discuss in later sections. The DM9013 will filter incoming packets under following conditions: (1). Error packets, including CRC errors, alignment errors, illegal size errors. Preliminary datasheet DM9013-15-DS-P03 April 9, 2009 (2). PAUSE packets. (3). If incoming packet is UNICAST and its destination port number is equal to source port number. 9.2.4 Inter-Packet Gap (IPG) IPG is the idle time between any two valid packets at the same port. The typical number is 96 bits time. In other word, the value is 9.6u sec for 10Mbps and 960n sec for 100Mbps. 9.2.5 Back-off Algorithm The DM9013 implements the binary exponential back-off algorithm in half-duplex mode compliant to IEEE standard 802.3. 9.2.6 Late Collision Late Collision is a type of collision. If a collision error occurs after the first 512 bit times of data are transmitted, the packet is dropped. 9.2.7 Full Duplex Flow Control The DM9013 supports IEEE standard 802.3x flow control frames on both transmit and receive sides. On the receive side, The DM9013 will defer transmitting next normal frames, if it receives a pause frame from link partner. On the transmit side, The DM9013 issues pause frame with maximum pause time when internal resources such as received buffers, transmit queue and transmit descriptor ring are unavailable. Once resources are available, The DM9013 sends out a pause frame with zero pause time allows traffic to resume immediately. 9.2.8 Half Duplex Flow Control The DM9013 supports half-duplex backpressure. The inducement is the same as full duplex mode. When flow control is required, the DM9013 sends jam pattern, thus forcing a collision. The flow control ability can be set in bit 4 of register 61h. 9.2.9 Partition Mode The DM9013 provides a partition mode for each 55 DM9013 3-port switch with Processor Interface port, see bit 6 of register 61h. The port enters partition mode when more than 64 consecutive collisions are occurred. In partition mode the port continuous to transmit but it will not receive. The port returned to normal operation mode when a good packet is seen on the wire. The detail description of partition mode represent following: (1). Entering Partition State A port will enter the Partition State when either of the following conditions occurs: The port detects a collision on every one of 64 consecutive re-transmit attempts to the same packet. The port detects a single collision which occurs for more than 512 bit times. Transmit defer timer time out, which indicates the transmitting packet is deferred to long. (2). While in Partition state: The port will continue to transmit its pending packet, regardless of the collision detection, and will not allow the usual Back-off Algorithm. Additional packets pending for transmission will be transmitted, while ignoring the internal collision indication. This frees up the ports transmit buffers which would otherwise be filled up at the expense of other ports buffers. The assumption is that the partition is signifying a system failure situation (bad connection/cable/station), thus dropping packets is a small price to pay vs. the cost of halting the switch due to a buffer full condition. (3). Exiting from Partition State The Port exits from Partition State, following the end of a successful packet transmission. A successful packet transmission is defined as no collisions were detected on the first 512 bits of the transmission. 9.2.10 Broadcast Storm Filtering The DM9013 has an option to limit the traffic of broadcast or multicast packets, to protect the switch from lower bandwidth availability. There are two type of broadcast storm control, one is throttling broadcast packet only, the other includes multicast. This feature can be set through bit 1 of register 61h. The broadcast storm threshold can be programmed by EEPROM or register 67h, the default setting is no broadcast storm protecting. 56 9.2.11 Bandwidth Control The DM9013 supports two type of bandwidth control for each port. One is the ingress and egress bandwidth rate can be control separately, the other is combined together, this function can be set through bit 3 of register 61h. The bandwidth control is disabled by default. For separated bandwidth control mode, the threshold rate is defined in register 66h. For combined mode, it is defined in register 67h. The behavior of bandwidth control as below: (1).For the ingress control, if flow control function is enabled, Pause or Jam packet will be transmitted. The ingress packets will be dropped if flow control is disabled. (2).For the egress control, the egress port will not transmit any packets. On the other hand, the ingress bandwidth of source port will be throttled that prevent packets from forwarding. (3).In combined mode, if the sum of ingress and egress bandwidth over threshold, the bandwidth will be throttled. 9.2.12 Port Monitoring Support The DM9013 supports "Port Monitoring" function on per port base, detail as below: (1). Sniffer Port and Monitor Port There is only one port can be selected as "sniffer port" by register 52h, multiple ports can be set as "receive monitor port" or "transmit monitor port" in per-port register 65h. (2).Receive monitor All packets received on the "receive monitor port" are send a copy to "sniffer port". For example, port 0 is set as "receive monitor port" and port 3 is selected as "sniffer port". If a packet is received form port 0 and predestined to port 1 after forwarding decision, the DM9013 will forward it to port 1 and port 3 in the end. (3).Transmit monitor All packets transmitted on the "transmit monitor port" are send a copy to "sniffer port". For example, port 1 is set as "transmit monitor port" and port 3 is selected as "sniffer port". If a packet is received from port 0 and predestined to port 1 after forwarding decision, the DM9013 will forward it to port 1 and port 3 in the end. Preliminary datasheet DM9013-15-DS-P03 April 9, 2009 DM9013 3-port switch with Processor Interface (4).Exception The DM9013 has an optional setting that broadcast/multicast packets are not monitored (see bit 4 of register 65h). It's useful to avoid unnecessary bandwidth. (1). Set PVID of Port 0 to 0x01h. (2). Set PVID of Port 1 to 0x02h. (3). Set PVID of Port 2 to 0x03h. (4). Set PVID of Port 3 to 0x04h. (5). Set register B1h to 0x02h. (6). Set register B2h to 0x05h. (7). Set register B3h to 0x0Ah. (8). Set register B4h to 0x04h. 9.2.13.2 802.1Q-Based VLAN Regarding IEEE 802.1Q standard, Tag-based VLAN uses an extra tag to identify the VLAN membership of a frame across VLAN-aware switch/router. A tagged frame is four bytes longer than an untagged frame and contains two bytes of TPID (Tag Protocol Identifier) and two bytes of TCI (Tag Control Information). 9.2.13 VLAN Support 9.2.13.1 Port-Based VLAN The DM9013 supports port-based VLAN as default, up to 16 groups. Each port has a default VID called PVID (Port VID, see register 6Fh). The DM9013 used LSB 4-bytes of PVID as index and mapped to register B0h~BFh, to define the VLAN groups. For instance, we intend to partition DM9013's ports into three groups. Port 0 and port 1 in group A, port 1 and port 2 in group B, finally, port 2 and port 3 in group C. In this case, the setting as below: Dest. Src. Length/Type Data Standard frame Dest. Src. TPID 0x8100 2 bytes TCI Length / Type Data Tagged frame Priority 3 bits The DM9013 also supports 16 802.1Q-based VLAN groups, as specified in bit 1 of register 53h. It's obvious that the tagged packets can be assigned to several different VLANs which are determined according to the VID inside the VLAN Tag. Therefore, the operation is similar to port-based VLAN. The DM9013 used LSB 4-bytes VID of received packet with VLAN tag and VLAN Group Mapping Register (B0h~BFh) to configure the VLAN partition. If the destination port of received packet is not same VLAN group with received port, it will be discarded. CFI 1 bits VID VLAN_9013.vsd 12 bits 9.2.13.3 Tag/Untag User can define each port as Tag port or Un-tag port by bit 7 of register 6Dh in 802.1Q-based VLAN mode. The operation of Tag and Un-tag can explain as below conditions: (1). Receive untagged packet and forward to Un-tag port. Received packet will forward to destination port without modification. (2). Receive tagged packet and forward to Un-tag port. The DM9013 will remove the tag from the packet and recalculate CRC before sending it out. 57 Preliminary datasheet DM9013-15-DS-P03 April 9, 2009 DM9013 3-port switch with Processor Interface (3). Receive untagged packet and forward to Tag port. The DM9013 will insert the PVID tag when an untagged packet enters the port, and recalculate CRC before delivering it. (4). Receive tagged packet and forward to Tag port. Received packet will forward to destination port without modification. 9.2.14 Priority Support The DM9013 supports Quality of Service (QoS) mechanism for multimedia communication such as VoIP and video conferencing. The DM9013 provides three priority classifications: Port-based, 802.1p-based and DiffServ-based priority. See next section for more detail. The DM9013 offers four level queues for transmit on per-port based. The DM9013 provides two packet scheduling algorithms: Strict Priority Queuing. based on their priority and queue weight. Queues with larger weights get more service than smaller. This mechanism can get highly efficient bandwidth and smooth the traffic. Strict Priority Queuing (SPQ) based on priority only. The Packet on the highest priority queue is transmitted first. The next highest-priority queue is work until last queue empties, and so on. This feature can be set in bit 5 of register 6Dh. 9.2.14.1 Port-Based Priority Port based priority is the simplest scheme and as default. Each port has a 2-bit priority value as index for splitting ingress packets to the corresponding transmit queue. This value can be set in bit 0 and 1 of register 6Dh. 9.2.14.2 802.1p-Based Priority 802.1p priority can be disabled by bit 2 of register 6Dh, it is enabled by default. The DM9013 extracts 3-bit priority field from received packet with 802.1p VLAN tag, and maps this field against VLAN Priority Map Registers (D0h~D1h) to determine which transmit queue is designated. The VLAN Priority Map is programmable. 9.2.14.3 DiffServ-Based Priority DiffServ based priority uses the most significant 6-bit of the ToS field in standard IPv4 header, and maps this field against ToS Priority Map Registers (C0h~CFh) to determine which transmit queue is designated. The ToS Priority Map is programmable too. In addition, User can only refer to most significant 3-bit of the ToS field optionally, see bit 7 of register 53h. 58 Preliminary datasheet DM9013-15-DS-P03 April 9, 2009 DM9013 3-port switch with Processor Interface 9.3 MII Interface 9.3.1 MII data interface The DM9013 port 2 provides a Media Independent Interface (MII) as defined in the IEEE 802.3u standard (Clause 22). The MII consists of a nibble wide receive data bus, a nibble wide transmit data bus, and control signals to facilitate data transfers between the DM9013 port 2 and external device (a PHY or a MAC in reverse MII). * TXD2 (transmit data) is a nibble (4 bits) of data that are driven by the DM9013 synchronously with respect to TXC2. For each TXC2 period, which TXE2 is asserted, TXD2 (3:0) are accepted for transmission by the external device. * TXC2 (transmit clock) from the external device is a continuous clock that provides the timing reference for the transfer of the TXE2, TXD2. The DM9013 can drive 25MHz clock if it is configured to reversed MII mode. * TXE2 (transmit enable) from the DM9013 port 2 MAC indicates that nibbles are being presented on the MII for transmission to the external device. * RXD2 (receive data) is a nibble (4 bits) of data that are sampled by the DM9013 port 2 MAC synchronously with respect to RXC2. For each RXC2 period which RXDV2 is asserted, RXD2 (3:0) are transferred from the external device to the DM9013 port 2 MAC reconciliation sub layer. * RXC2 (receive clock) from external device to the DM9013 port 2 MAC reconciliation sub layer is a continuous clock that provides the timing reference for the transfer of the RXDV2, RXD2, and RXER2 signals. * RXDV2 (receive data valid) input from the external device to indicates that the external device is presenting recovered and decoded nibbles to the DM9013 port 2 MAC reconciliation sub layer. To interpret a receive frame correctly by the reconciliation sub layer, RXDV2 must encompass the frame, starting no later than the Start-of-Frame delimiter and excluding any End-Stream delimiter. * RXER2 (receive error) input from the external device is synchronously with respect to RXC2. RXER2 will be asserted for 1 or more clock periods to indicate to the reconciliation sub layer that an error was detected somewhere in the frame being Preliminary datasheet DM9013-15-DS-P03 April 9, 2009 transmitted from the external device to the DM9013 port 2 MAC. * CRS2 (carrier sense) is asserted by the external device when either the transmit or receive medium is non-idle, and de-asserted by the external device when the transmit and receive medium are idle. The CRS2 can also in output mode when the DM9013 port 2 is configured to reversed MII mode. * COL2 (collision detection) is asserted by the external device, when both the transmit and receive medium is non-idle, and de-asserted by the external device when the either transmit or receive medium are idle. The COL2 can also in output mode when the DM9013 port 2 is configured to reversed MII mode. 9.3.2 MII Serial Management The MII serial management interface consists of a data interface, basic register set in DM9013 port 0 and 1, and a serial management interface to the register set. Through this interface it is possible to control and configure multiple PHY devices, include internal two ports, get status and error information, and determine the type and capabilities of the attached PHY device(s). The DM9013 default is polling 3 ports basic registers 0, 1, 4, and 5 to get the link, duplex, and speed status automatically. Alternatively, the DM9013 can be programmed to read or write any registers of 3 ports by section 6.8~11 CSR B, C, D, and E. The DM9013 management functions correspond to MII specification for IEEE 802.3u-1995 (Clause 22) for registers 0 through 6 with vendor-specific registers 16,17, 18, 21, 22, 23 and 24~27. In read/write operation, the management data frame is 64-bits long and starts with 32 contiguous logic one bits (preamble) synchronization clock cycles on MDC. The Start of Frame Delimiter (SFD) is indicated by a <01> pattern followed by the operation code (OP) :< 10> indicates Read operation and <01> indicates Write operation. For read operation, a 2-bit turnaround (TA) filing between Register Address field and Data field is provided for MDIO to avoid contention. Following the turnaround time, 16-bit data is read from or written onto management registers. 59 DM9013 3-port switch with Processor Interface 9.3.3 Serial Management Interface The serial control interface uses a simple two-wired serial interface to obtain and control the status of the physical layer through the MII interface. The serial control interface consists of MDC (Management Data Clock), and MDI/O (Management Data Input/Output) signals. The MDIO pin is bi-directional and may be shared by up to 32 devices. 9.3.4 Management Interface - Read Frame Structure MDC MDIO Read 32 "1"s Idle Preamble 0 SFD 1 1 0 A4 A3 PHY Address Write A0 R4 R3 R0 0 D15 D14 // Data Read // D1 D0 Idle Z Op Code Register Address Turn Around 9.3.5 Management Interface - Write Frame Structure MDC MDIO Write 32 "1"s Idle Preamble 0 SFD 1 0 1 A4 A3 PHY Address A0 R4 R3 R0 1 0 D15 D14 Data D1 D0 Idle Op Code Register Address Write Turn Around 60 Preliminary datasheet DM9013-15-DS-P03 April 9, 2009 DM9013 3-port switch with Processor Interface 9.4 Internal PHY functions 9.4.1 100Base-TX Operation The transmitter section contains the following functional blocks: - 4B5B Encoder - Scrambler - Parallel to Serial Converter - NRZ to NRZI Converter - NRZI to MLT-3 - MLT-3 Driver 9.4.1.1 4B5B Encoder The 4B5B encoder converts 4-bit (4B) nibble data generated by the MAC Reconciliation Layer into a 5-bit (5B) code group for transmission, see reference Table 1. This conversion is required for control and packet data to be combined in code groups. The 4B5B encoder substitutes the first 8 bits of the MAC preamble with a J/K code-group pair (11000 10001) upon transmit. The 4B5B encoder continues to replace subsequent 4B preamble and data nibbles with corresponding 5B code-groups. At the end of the transmit packet, upon the deassertion of the Transmit Enable signal from the MAC Reconciliation layer, the 4B5B encoder injects the T/R code-group pair (01101 00111) indicating the end of frame. After the T/R code-group pair, the 4B5B encoder continuously injects IDLEs into the transmit data stream until Transmit Enable is asserted and the next transmit packet is detected. By scrambling the data, the total energy presented to the cable is randomly distributed over a wide frequency range. Without the scrambler, energy levels on the cable could peak beyond FCC limitations at frequencies related to the repeated 5B sequences, like the continuous transmission of IDLE symbols. The scrambler output is combined with the NRZ 5B data from the code-group encoder via an XOR logic function. The result is a scrambled data stream with sufficient randomization to decrease radiated emissions at critical frequencies. 9.4.1.3 Parallel to Serial Converter The Parallel to Serial Converter receives parallel 5B scrambled data from the scrambler, and serializes it (converts it from a parallel to a serial data stream). The serialized data stream is then presented to the NRZ to NRZI encoder block 9.4.1.4 NRZ to NRZI Encoder After the transmit data stream has been scrambled and serialized, the data must be NRZI encoded for compatibility with the TP-PMD standard, for 100Base -TX transmission over Category-5 unshielded twisted pair cable. 9.4.1.5 MLT-3 Converter The MLT-3 conversion is accomplished by converting the data stream output, from the NRZI encoder into two binary data streams, with alternately phased logic one event. 9.4.1.6 MLT-3 Driver The two binary data streams created at the MLT-3 converter are fed to the twisted pair output driver, which converts these streams to current sources and alternately drives either side of the transmit transformer's primary winding, resulting in a minimal current MLT-3 signal. 9.4.1.2 Scrambler The scrambler is required to control the radiated emissions (EMI) by spreading the transmit energy across the frequency spectrum at the media connector and on the twisted pair cable in 100Base-TX operation. Preliminary datasheet DM9013-15-DS-P03 April 9, 2009 61 DM9013 3-port switch with Processor Interface 9.4.1.7 4B5B Code Group Symbol 0 1 2 3 4 5 6 7 8 9 A B C D E F I J K T R H V V V V V V V V V V Meaning Data 0 Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 Data 8 Data 9 Data A Data B Data C Data D Data E Data F Idle SFD (1) SFD (2) ESD (1) ESD (2) Error Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid 4B code 3210 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 undefined 0101 0101 undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined Table 1 5B Code 43210 11110 01001 10100 10101 01010 01011 01110 01111 10010 10011 10110 10111 11010 11011 11100 11101 11111 11000 10001 01101 00111 00100 00000 00001 00010 00011 00101 00110 01000 01100 10000 11001 62 Preliminary datasheet DM9013-15-DS-P03 April 9, 2009 DM9013 3-port switch with Processor Interface 9.4.2 100Base-TX Receiver The 100Base-TX receiver contains several function blocks that convert the scrambled 125Mb/s serial data to synchronous 4-bit nibble data. The receive section contains the following functional blocks: - Signal Detect - Digital Adaptive Equalization - MLT-3 to Binary Decoder - Clock Recovery Module - NRZI to NRZ Decoder - Serial to Parallel - Descrambler - Code Group Alignment - 4B5B Decoder 9.4.2.1 Signal Detect The signal detects function meets the specifications mandated by the ANSI XT12 TP-PMD 100Base-TX standards for both voltage thresholds and timing parameters. 9.4.2.2 Adaptive Equalization When transmitting data over copper twisted pair cable at high speed, attenuation based on frequency becomes a concern. In high speed twisted pair signaling, the frequency content of the transmitted signal can vary greatly during normal operation based on the randomness of the scrambled data stream. This variation in signal attenuation, caused by frequency variations, must be compensated for to ensure the integrity of the received data. In order to ensure quality transmission when employing MLT-3 encoding, the compensation must be able to adapt to various cable lengths and cable types depending on the installed environment. The selection of long cable lengths for a given implementation requires significant compensation, which will be over-killed in a situation that includes shorter, less attenuating cable lengths. Conversely, the selection of short or intermediate cable lengths requiring less compensation will cause serious under-compensation for longer length cables. Therefore, the compensation or equalization must be adaptive to ensure proper conditioning of the received signal independent of the cable length. Preliminary datasheet DM9013-15-DS-P03 April 9, 2009 9.4.2.3 MLT-3 to NRZI Decoder The DM9013 decodes the MLT-3 information from the Digital Adaptive Equalizer into NRZI data. 9.4.2.4 Clock Recovery Module The Clock Recovery Module accepts NRZI data from the MLT-3 to NRZI decoder. The Clock Recovery Module locks onto the data stream and extracts the 125 MHz reference clock. The extracted and synchronized clock and data are presented to the NRZI to NRZ decoder. 9.4.2.5 NRZI to NRZ The transmit data stream is required to be NRZI encoded for compatibility with the TP-PMD standard for 100Base-TX transmission over Category-5 unshielded twisted pair cable. This conversion process must be reversed on the receive end. The NRZI to NRZ decoder receives the NRZI data stream from the Clock Recovery Module and converts it to a NRZ data stream to be presented to the Serial to Parallel conversion block. 9.4.2.6 Serial to Parallel The Serial to Parallel Converter receives a serial data stream from the NRZI to NRZ converter. It converts the data stream to parallel data to be presented to the descrambler. 9.4.2.7 Descrambler Because of the scrambling process requires to control the radiated emissions of transmit data streams, the receiver must descramble the receive data streams. The descrambler receives scrambled parallel data streams from the Serial to Parallel converter, and it descrambles the data streams, and presents the data streams to the Code Group alignment block. 63 DM9013 3-port switch with Processor Interface 9.4.2.8 Code Group Alignment The Code Group Alignment block receives un-aligned 5B data from the descrambler and converts it into 5B code group data. Code Group Alignment occurs after the J/K is detected and subsequent data is aligned on a fixed boundary. 9.4.2.9 4B5B Decoder The 4B5B Decoder functions as a look-up table that translates incoming 5B code groups into 4B (Nibble) data. When receiving a frame, the first 2 5-bit code groups receive the start-of-frame delimiter (J/K symbols). The J/K symbol pair is stripped and two nibbles of preamble pattern are substituted. The last two code groups are the end-of-frame delimiter (T/R Symbols). The T/R symbol pair is also stripped from the nibble, presented to the Reconciliation layer. 9.4.3 10Base-T Operation The 10Base-T transceiver is IEEE 802.3u compliant. When the DM9013 is operating in 10Base-T mode, the coding scheme is Manchester. Data processed for transmit is presented in nibble format, converted to a serial bit stream, then the Manchester encoded. When receiving, the bit stream, encoded by the Manchester, is decoded and converted into nibble format. 9.4.4 Collision Detection For half-duplex operation, a collision is detected when the transmit and receive channels are active simultaneously. Collision detection is disabled in full duplex operation. 9.4.5 Carrier Sense Carrier Sense (CRS) is asserted in half-duplex operation during transmission or reception of data. During full-duplex mode, CRS is asserted only during receive operations. 9.4.6 Auto-Negotiation The objective of Auto-negotiation is to provide a means to exchange information between linked devices and to automatically configure both devices to take maximum advantage of their abilities. It is important to note that Auto-negotiation does not test the characteristics of the linked segment. The Auto-Negotiation function provides a means for a device to advertise supported modes of operation to a remote link partner, acknowledge the receipt and understanding of common modes of operation, and to reject un-shared modes of operation. This allows devices on both ends of a segment to establish a link at the best common mode of operation. If more than one common mode exists between the two devices, a mechanism is provided to allow the devices to resolve to a single mode of operation using a predetermined priority resolution function. Auto-negotiation also provides a parallel detection function for devices that do not support the Auto-negotiation feature. During Parallel detection there is no exchange of information of configuration. Instead, the receive signal is examined. If it is discovered that the signal matches a technology, which the receiving device supports, a connection will be automatically established using that technology. This allows devices not to support Auto-negotiation but support a common mode of operation to establish a link. 64 Preliminary datasheet DM9013-15-DS-P03 April 9, 2009 DM9013 3-port switch with Processor Interface 10. DC and AC Electrical Characteristics 10.1 Absolute Maximum Ratings Symbol Parameter VCC3 3.3V Supply Voltage VCCI 1.8V core power supply AVDD3 Analog power supply 3.3V AVDDI Analog power supply 1.8V VIN DC Input Voltage (VIN) Storage Temperature range TSTG Ambient Temperature TA Lead Temperature LT (TL, soldering, 10 sec.). 10.2 Operating Conditions Symbol Parameter VCC3 3.3V Supply Voltage VCCI 1.8V core power supply AVDD3 Analog power supply 3.3V AVDDI Analog power supply 1.8V PD 100BASE-TX (Power Dissipation) 10BASE-TX Min. -0.3 -0.3 -0.3 -0.3 -0.5 -65 0 Max. 3.6 1.95 3.6 1.95 5.5 +150 +70 +260 Unit V V V V V C C C Conditions Lead-free Device Min. 3.135 1.71 3.135 1.71 - Max. 3.465 1.89 3.465 1.89 230 70 140 250 360 30 170 40 Unit V V V V mA mA mA mA mA mA mA mA Conditions Auto-negotiation or cable off 1.8V only 3.3V only TX idle, 1.8V only 50% utilization, 1.8V only 100% utilization, 1.8V only 3.3V only 1.8V only 3.3V only Preliminary datasheet DM9013-15-DS-P03 April 9, 2009 65 DM9013 3-port switch with Processor Interface 10.3 DC Electrical Characteristics Symbol Parameter Inputs VIL Input Low Voltage VIH Input High Voltage IIL Input Low Leakage Current IIH Input High Leakage Current Outputs VOL Output Low Voltage VOH Output High Voltage Receiver VICM RX+/RX- Common Mode Input Voltage Transmitter VTD100 100TX+/- Differential Output Voltage VTD10 10TX+/- Differential Output Voltage ITD100 100TX+/- Differential Output Current ITD10 10TX+/- Differential Output Current Min. 2.0 -1 2.4 Typ. 1.8 Max. 0.8 1 0.4 Unit V V uA uA V V V Conditions Vcond1 Vcond1 VIN = 0.0V, Vcond1 VIN = 3.3V, Vcond1 IOL = 4mA IOH = -4mA 100 Termination Across Peak to Peak Peak to Peak Absolute Value Absolute Value 1.9 4.4 19 44 2.0 5 20 50 2.1 5.6 21 56 V V mA mA Note: Vcond1 = VCC3 = 3.3V, VCCI = 1.8V, AVDD3 = 3.3V, AVDDI = 1.8V. 10.4 AC characteristics 10.4.1 Power On Reset Timing T1 PWRST# T4 Strap pins T2 EECS T3 CS# T5 Symbol T1 T2 T3 T4 T5 66 Parameter PWRST# Low Period Strap pin hold time with PWRST# PWRST# high to EECS high PWRST# high to EECS burst end PWRST# high to CS# available Min. 1 40 -- Typ. 5 -400 Max. 4 -- Unit ms ns us ms us Conditions Preliminary datasheet DM9013-15-DS-P03 April 9, 2009 DM9013 3-port switch with Processor Interface 10.4.2 Processor I/O Read Timing CS#,CMD T1 T2 IOR# T4 T3 SD0~31 T5 T6 ior_9013.vsd Parameter CS#,CMD valid to IOR# valid IOR# invalid to CS#,CMD invalid IOR# width IOR# invalid to next IOR#/IOW# valid When read DM9003 register T4 IOR# invalid to next IOR#/IOW# valid When read DM9003 memory with F0h register T3+T4 IOR# invalid to next IOR#/IOW# valid When read DM9003 memory with F2h register T5 System Data(SD) Delay time T6 IOR# invalid to System Data(SD) invalid Note: the Unit: clk is under the internal system clock 50MHz.. Symbol T1 T2 T3 T4 Min. 5 5 20 2 4 1 Typ. Max. Unit ns ns ns clk* clk* clk* 25 10 ns ns Preliminary datasheet DM9013-15-DS-P03 April 9, 2009 67 DM9013 3-port switch with Processor Interface 10.4.3 Processor I/O Write Timing CS#,CMD T1 T2 IOW# T3 T4 T5 SD0~31 T6 iow_9013.vsd Parameter CS#,CMD valid to IOW# valid IOW# Invalid to CS#,CMD Invalid IOW# Width IOW# Invalid to next IOW#/IOR# valid When write DM9013 INDEX port T4 IOW# Invalid to next IOW#/IOR# valid When write DM9013 DATA port T5 System Data(SD) Hold Time T6 System Data(SD) Setup Time T3+T4 IOW# Invalid to next IOW#/IOR# valid When write DM9013 memory Note: the Unit: clk is under the internal system clock 50MHz. Symbol T1 T2 T3 T4 Min. 5 0 20 1 2 3 5 1 Typ. Max. Unit ns ns ns clk* clk* ns ns clk* 68 Preliminary datasheet DM9013-15-DS-P03 April 9, 2009 DM9013 3-port switch with Processor Interface 10.4.4 Port 2 MII Interface Transmit Timing TXC2 TXE2 T1 TXD2_3~0 MIITX_9013.vsd T2 Symbol Parameter T1 TXE2,TXD2_3~0 Setup Time T2 TXE2,TXD2_3~0 Hold Time Min. Typ. 32 8 Max. Unit ns ns 10.4.5 Port 2 MII Interface Receive Timing RXC2 RXER2,RXDV2 T1 RXD2_3~0 MIIRX_9013.vsd T2 Symbol Parameter T1 RXER2, RXDV2,RXD2_3~0 Setup Time T2 RXER2, RXDV2,RXD2_3~0 Hold Time Min. 5 5 Typ. Max. Unit ns ns Preliminary datasheet DM9013-15-DS-P03 April 9, 2009 69 DM9013 3-port switch with Processor Interface 10.4.6 MII Management Interface Timing T1 MDC T2 MDIO (drived by DM9013) T3 MDIO (drived by exetrnal MII) T5 MDIO_9013.vsd T4 Symbol T1 T2 T3 T4 T5 Parameter MDC Frequency MDIO by DM9013 Setup Time MDIO by DM9013 Hold Time MDIO by External MII Setup Time MDIO by External MII Hold Time Min. Typ. 0.52 955 960 Max. 40 40 Unit MHz ns ns ns ns 10.4.7 EEPROM Timing T1 EECS T3 EECK T4 EEDO T5 EEDI T7 eeprom_9013.vcd T2 T6 Symbol T1 T2 T3 T4 T5 T6 T7 Parameter EECS Setup Time EECS Hold Time EECK Frequency EEDO Setup Time EEDO Hold Time EEDI Setup Time EEDI Hold Time Min. Typ. 480 2080 0.38 460 2100 Max. 8 8 Unit ns ns MHz ns ns ns ns 70 Preliminary datasheet DM9013-15-DS-P03 April 9, 2009 DM9013 3-port switch with Processor Interface 11. Application circuit DVDD_33V DVDD_18V DVDD_33V DVDD_33V R3 C1 220uF C2 0.1uF C4 0.1uF C5 0.1uF C6 0.1uF C7 0.1uF C8 0.1uF C9 0.1uF C10 0.1uF C11 220uF C12 0.1uF C13 0.1uF C14 0.1uF EECK EEDO AVDD_33V AVDD_18V DVDD_33V 3 2 1 HEADER_3 J12 HEADER_3 4.7k J13 3 2 1 TXD2_3 GP6 GP5 TXD2_0 TXD2_1 TXD2_2 GP4 GP3 GP2 MDC TXE2 EECS MDIO 1.4K/1% R2 TEST2 RX0+ RX0TX0+ TX0RX1+ RX1TX1+ TX1RXDV2 RXD2_3 RXD2_2 RXD2_1 RXD2_0 CRS2 COL2 RXER2 RXC2 AVDD_33V AVDD_18V AVDD_18V DVDD_18V DVDD_33V J7 1 J8 1 2 JUMPER 2 JUMPER 1 J3 J4 1 J5 1 J16 1 J17 1 1 J6 2 JUMPER 2 JUMPER 2 JUMPER 2 JUMPER 2 JUMPER 2 JUMPER R5 4.7k IO16 IOWAIT R6 R36 R33 R7 R? R8 R? R9 R? R10 R11 R34 R35 4.7k 4.7k 4.7k NC(4.7K) 4.7k NC(4.7K) 4.7k NC(4.7K) 4.7k 4.7k 4.7k NC(4.7K) 4.7k uP Interface SD0 SD1 SD2 SD3 SD4 SD5 SD6 SD7 SD8 SD9 SD10 SD11 SD12 SD13 SD14 SD15 PWRST# CMD CS# IOW# IOR# IRQ IO16 IOWAIT WOL SD16 SD17 SD18 SD19 SD20 SD21 SD22 SD23 SD24 SD25 SD26 SD27 SD28 SD29 SD30 SD31 SD[00..31] SD[00..31] TEST2 C16 220uF C17 0.1uF C19 0.1uF C20 0.1uF C21 220uF C22 0.1uF C23 0.1uF DVDD_33V L1 AVDD_33V F.B/120/SO805 VCNTL 2SB1386 B E Q1 C DVDD_18V L2 PWRST# CMD CS# IOW# IOR# IRQ IO16 IOWAIT WOL F.B/120/SO805 C27 0.1uF C15 0.1uF L3 F.B/120/SO805 VREF C25 0.1uF Y1 J14 1 2 3 4 5 6 7 HEADER_7 SCLK 1 GP0 GP1 GP2 GP3 GP4 GP5 GP6 25MHz/49US C29 C30 22pF 22pF TP / LED Interface U3 TX0+ TX0RX0+ RX0TX1+ TX1RX1+ RX1LNK0_LED SPD0_LED FDX0_LED LNK1_LED SPD1_LED FDX1_LED BWLED[0..7] BWLED0 BWLED1 BWLED2 BWLED3 BWLED4 BWLED5 BWLED6 BWLED7 TX0+ TX0RX0+ RX0TX1+ TX1RX1+ RX1LNK0_LED SPD0_LED FDX0_LED LNK1_LED SPD1_LED FDX1_LED BWLED[0..7] BGRESG BGRES AVDD33 RX0RX0+ AGND AGND TX0TX0+ AVDD18 AVDD33 RX1RX1+ AGND AGND TX1TX1+ AVDD18 TEST3 TEST2 TEST1 DVDD33 RXD2_0 RXD2_1 RXD2_2 RXD2_3 RXDV2 GND RXC2 RXER2 COL2 CRS2 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 VCNTL VREF X1 X2 LNK1_LED SPD1_LED FDX1_LED LNK0_LED SPD0_LED FDX0_LED WOL GP6 GP5 GP4 GP3 GP2 SCLK GP1 GP0 BWLED0 BWLED1 BWLED2 BWLED3 BWLED4 BWLED5 BWLED6 BWLED7 J15 TEST_POINT EEPROM EECS EECK EEDO EEDI J9 1 U4 2 JUMPER 1 2 CS VCC DC 3 SK 4 DI ORG DO GND 93LC46 DVDD_33V DVDD_33V 3 8 7 6 5 DVDD_33V C31 0.1uF 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 CMD CS# IOW# DVDD33 IOR# IRQ SD0 SD1 SD2 SD3 GND SD4 SD5 SD6 SD7 SD8 SD9 DVDD33 SD10 SD11 GND SD12 SD13 DVDD18 SD14 SD15 GND SD16 (GP2_0) SD17 (GP2_1) SD18 (GP2_2) SD19 (GP2_3) DVDD33 VCNTL VREF AVDD33 DVDD33 X1 X2 GND LNK1_LED SPD1_LED FDX1_LED LNK0_LED SPD0_LED FDX0_LED WOL GP6 GP5 GP4 GP3 GP2 SCLK GP1 GP0 BWLED0 DVDD18 BWLED1 BWLED2 BWLED3 BWLED4 GND BWLED5 BWLED6 BWLED7 DM9013E for uP Interface 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 TXC2 TXE2 VCC3 TXD2_0 TXD2_1 TXD2_2 TXD2_3 DVDD18 MDIO MDC GND PWRST# EECS EECK EEDO EEDI DVDD33 (GP3_7) SD31 (GP3_6) SD30 GND (GP3_5) SD29 (GP3_4) SD28 (GP3_3) SD27 (GP3_2) SD26 DVDD33 (GP3_1) SD25 (GP3_0) SD24 (GP2_7) SD23 (GP2_6) SD22 GND (GP2_5) SD21 (GP2_4) SD20 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 TXC2 TXE2 TXD2_0 TXD2_1 TXD2_2 TXD2_3 MDIO MDC PWRST# EECS EECK EEDO EEDI SD31 SD30 SD29 SD28 SD27 SD26 SD25 SD24 SD23 SD22 SD21 SD20 MII Interface RXD2_0 RXD2_1 RXD2_2 RXD2_3 RXDV2 RXC2 CRS2 COL2 RXER2 RXD2_[0..3] RXD2_[0..3] RXDV2 RXC2 CRS2 COL2 RXER2 TXD2_[0..3] TXD2_[0..3] R12 10K A D1 1N4148 U10 RESET_IC_(AP1701DW) 1 3 2 C TXD2_0 TXD2_1 TXD2_2 TXD2_3 TXE2 TXC2 MDIO MDC TXE2 TXC2 MDIO MDC 1 2 PWRST# Title Size B Date: Davicom Semiconductor Inc. C32 CMD CS# IOW# IOR# IRQ SD0 SD1 SD2 SD3 SD16 SD17 SD18 SD19 SD10 SD11 SD12 SD13 SD14 SD15 10uF SD4 SD5 SD6 SD7 SD8 SD9 MAIN_CHIP Document Number DM9013E_EVB_BOARD Tuesday , December 19, 2006 Sheet 1 of 3 Rev 2.1 Preliminary datasheet DM9013-15-DS-P03 April 9, 2009 71 DM9013 3-port switch with Processor Interface MII Interface RXD2_0 RXD2_1 RXD2_2 RXD2_3 RXDV2 RXC2 CRS2 COL2 RXER2 TXD2_[0..3] TXD2_0 TXD2_1 TXD2_2 TXD2_3 TXE2 TXC2 MDIO MDC DVDD_5V RXD2_[0..3] I U5 IN AP1117-3.3V O OUT OUT 4 C33 220uF C34 0.1uF RXD2_0 RXD2_1 RXD2_2 RXD2_3 CRS2 COL2 RXDV2 RXER2 RXC2 TXC2 TXD2_0 TXD2_1 TXD2_2 TXD2_3 MDIO DVDD_33V RXD2_[0..3] RXDV2 RXC2 CRS2 COL2 RXER2 TXD2_[0..3] G GND TXE2 TXC2 MDIO MDC TXE2 MDC WOL uP Interface SD0 SD1 SD2 SD3 SD4 SD5 SD6 SD7 SD8 SD9 SD10 SD11 SD12 SD13 SD14 SD15 PWRST# CMD CS# IOW# IOR# IRQ IO16 IOWAIT WOL SD16 SD17 SD18 SD19 SD20 SD21 SD22 SD23 SD24 SD25 SD26 SD27 SD28 SD29 SD30 SD31 SD[00..31] SD[00..31] DVDD_5V IOWAIT CS# CMD IRQ PWRST# IOW# IOR# IO16 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 PWRST# CMD CS# IOW# IOR# IRQ IO16 IOWAIT WOL Davicom Semiconductor Inc. Title Size A Date: CONNECT_AND_POWER Document Number 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 SD0 SD1 SD2 SD3 SD4 SD5 SD6 SD7 SD8 SD9 SD10 SD11 SD12 SD13 SD14 SD15 Rev 2.1 2 of 3 Sheet J11 HEADER_16 DM9013E_EVB_BOARD Tuesday , December 19, 2006 72 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 JP2 HEADER_16X2 SD16 SD17 SD18 SD19 SD20 SD21 SD22 SD23 SD24 SD25 SD26 SD27 SD28 SD29 SD30 SD31 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 DVDD_5V DVDD_33V 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 JP1 HEADER_16X2 Preliminary datasheet DM9013-15-DS-P03 April 9, 2009 DM9013 3-port switch with Processor Interface TP / LED Interface TX0+ TX0RX0+ RX0TX1+ TX1RX1+ RX1TX0+ TX0RX0+ RX0TX1+ TX1RX1+ RX1LNK0_LED SPD0_LED FDX0_LED LNK1_LED SPD1_LED FDX1_LED BWLED[0..7] BWLED0 BWLED1 BWLED2 BWLED3 BWLED4 BWLED5 BWLED6 BWLED7 SPD0_LED DVDD_33V LNK0_LED SPD0_LED FDX0_LED C D3 C D2 LEDA C D4 LEDA LEDA 4 3 2 1 4 3 2 1 R22 330 LNK0_LED 5 6 7 8 5 6 7 8 3 74HC04 AVDD_18V RX1RX1+ TX1TX1+ DVDD_33V BWLED7 BWLED6 BWLED5 BWLED4 BWLED3 BWLED2 BWLED1 BWLED0 C D9 C D11 C D8 LEDA C D10 LEDA C D12 LEDA C D14 LEDA LEDA LEDA 4 3 2 1 4 3 2 1 R28 330 5 6 7 8 5 6 7 8 R24 49.9/1% R25 R26 R27 49.9/1% 49.9/1% 49.9/1% 1 2 3 4 5 6 7 8 JP4 RJ-45 RXNC RX+ MCT NC TXNC TX+ 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 4 1 BWLED[0..7] AVDD_18V RX0RX0+ TX0TX0+ R13 49.9/1% R14 R15 R16 49.9/1% 1 2 3 4 5 6 7 8 U6 RDNC RD+ NC CT TDNC TD+ RX+ NC RXMCT NC TX+ NC TX16 15 14 13 12 11 10 9 JP3 RJ-45_LED 1 2 3 4 5 6 7 8 LED2+ LED216 15 LNK0_LED SPD0_LED FDX0_LED LNK1_LED SPD1_LED FDX1_LED MAGCOM_HS9024 R17 R18 R19 75/1% 75/1% 75/1% C35 C38 0.1uF 0.01uF/2KV RJ45_SPD RJ45_LINK 74HC04 U2A 2 U2B 49.9/1% 49.9/1% C36 0.1uF C37 0.1uF R20 R21 512 512 LNK1_LED SPD1_LED FDX1_LED C D6 C D5 LEDA C D7 LEDA LEDA R23 330 U7 RDNC RD+ NC CT TDNC TD+ MAGCOM_HS9016 R29 R30 R31 75/1% 75/1% 75/1% C39 C42 0.1uF 0.01uF/2KV C D13 C D15 LEDA LEDA R32 330 C40 0.1uF C43 C41 0.1uF 0.1uF C44 Title Size A Date: Davicom Semiconductor Inc. RJ45_AND_LED Document Number 0.1uF DM9013E_EVB_BOARD Tuesday , December 19, 2006 Sheet 3 of 3 Preliminary datasheet DM9013-15-DS-P03 April 9, 2009 14 13 Rev 2.1 LED1+ LED1- 73 DM9013 3-port switch with Processor Interface 12. Package Information 128 Pins LQFP Package Outline Information: Symbol A A1 A2 b b1 c c1 D D1 E E1 E L L1 R1 R2 S 1 2 3 Dimension in mm Min 0.05 1.35 0.13 0.13 0.09 0.09 15.85 13.90 15.85 13.90 0.45 0.08 0.08 0.20 0 0 o o o o Dimension in inch Max 1.60 1.45 0.23 0.19 0.20 0.16 16.15 14.10 16.15 14.10 0.75 0.20 Min 0.002 0.053 0.005 0.005 0.004 0.004 0.624 0.547 0.624 0.547 0.018 0.003 0.003 0.008 0 o o o o Nom 1.40 0.18 0.16 16.00 14.00 16.00 14.00 0.40 BSC 0.60 1.00 REF 3.5 12 TYP 12 TYP o Nom 0.055 0.007 0.006 0.630 0.551 0.630 0.551 0.016 BSC 0.024 0.039 REF 3.5 12 TYP 12 TYP o Max 0.063 0.057 0.009 0.007 0.008 0.006 0.636 0.555 0.636 0.555 0.030 0.008 7 o 7 o - 0 - 1. Dimension D1 and E1 do not include resin fin. 2. All dimensions are base on metric system. 3. General appearance spec should base on its final visual inspection spec. 74 Preliminary datasheet DM9013-15-DS-P03 April 9, 2009 DM9013 3-port switch with Processor Interface 13. Ordering Information Part Number DM9013EP Pin Count 128 Package LQFP (Pb-free) application circuits illustrated in this document are for reference purposes only. DAVICOM's terms and conditions printed on the order acknowledgment govern all sales by DAVICOM. DAVICOM will not be bound by any terms inconsistent with these unless DAVICOM agrees otherwise in writing. Acceptance of the buyer's orders shall be based on these terms. Disclaimer The information appearing in this publication is believed to be accurate. Integrated circuits sold by DAVICOM Semiconductor are covered by the warranty and patent indemnification provisions stipulated in the terms of sale only. DAVICOM makes no warranty, express, statutory, implied or by description regarding the information in this publication or regarding the information in this publication or regarding the freedom of the described chip(s) from patent infringement. FURTHER, DAVICOM MAKES NO WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. DAVICOM reserves the right to halt production or alter the specifications and prices at any time without notice. Accordingly, the reader is cautioned to verify that the data sheets and other information in this publication are current before placing orders. Products described herein are intended for use in normal commercial applications. Applications involving unusual environmental or reliability requirements, e.g. military equipment or medical life support equipment, are specifically not recommended without additional processing by DAVICOM for such applications. Please note that Company Overview DAVICOM Semiconductor Inc. develops and manufactures integrated circuits for integration into data communication products. Our mission is to design and produce IC products that are the industry's best value for Data, Audio, Video, and Internet/Intranet applications. To achieve this goal, we have built an organization that is able to develop chipsets in response to the evolving technology requirements of our customers while still delivering products that meet their cost requirements. Products We offer only products that satisfy high performance requirements and which are compatible with major hardware and software standards. Our currently available and soon to be released products are based on our proprietary designs and deliver high quality, high performance chipsets that comply with modem communication standards and Ethernet networking standards. Contact Windows For additional information about DAVICOM products, contact the Sales department at: Headquarters Hsin-chu Office: No.6 Li-Hsin Rd. VI, Science-based Park, Hsin-chu City, Taiwan, R.O.C. TEL: + 886-3-5798797 FAX: + 886-3-5646929 MAIL: sales@davicom.com.tw HTTP: http://www.davicom.com.tw WARNING Conditions beyond those listed for the absolute maximum may destroy or damage the products. In addition, conditions for sustained periods at near the limits of the operating ranges will stress and may temporarily (and permanently) affect and damage structure, performance and/or function. Preliminary datasheet DM9013-15-DS-P03 April 9, 2009 75 |
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